Pin-En Su

12 papers Journal 8Unranked 4
YearRankTypeTitle / Venue / Authors
2017 J jnl
A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.
IEEE J. Solid State Circuits
Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori
2016 — conf
19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC.
ISSCC
Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori
2016 J jnl
A 2.7 mW/Channel 48-1000 MHz Direct Sampling Full-Band Cable Receiver.
IEEE J. Solid State Circuits
Jiangfeng Wu, Giuseppe Cusmai, Acer Wei-Te Chou, Tao Wang, Bo Shen, Vijayaramalingam Periasamy, Ming-Hung Hsieh, Chun-Ying Chen, Lin He, Loke Kun Tan, Aravind Padyana, Vincent Cheng-Hsun Yang, Gregory Unruh, Jackie Koon Lun Wong, Bryan Juo-Jung Hung, Massimo Brandolini, Maco Sha-Ting Lin, Xi Chen, Yen Ding, Yen-Jen Ko, Young J. Shin, Ada Hing T. Hung, Binning Chen, Cynthia Dang, Deepak Lakshminarasimhan, Iris Hong Liu, Jerry Lin, Kowen Lai, Larry Wassermann, Ayaskant Shrivastava, Chi-Ming Hsiao, Chun-Sheng Huang, Jianlong Chen, Lakshminarasimhan Krishnan, Ning-Yi Wang, Pin-En Su, Tianwei Li, Wei-Ta Shih, Yau-Cheng Yang, Peter Cangiane, Randall Perlow, William Ngai, Hanson Hung-Sen Huang, James Y. C. Chang, Xicheng Jiang, Ardie G. Venes, Ramon Ray Gomez
2015 — conf
A 2.7mW/Channel 48-to-1000MHz Direct Sampling Full-Band Cable Receiver.
VLSIC
Jiangfeng Wu, Giuseppe Cusmai, Acer Wei-Te Chou, Tao Wang, Bo Shen, Vijayaramalingam Periasamy, Ming-Hung Hsieh, Chun-Ying Chen, Lin He, Loke Tan, Aravind Padyana, Cheng-Hsun Yang, Gregory Unruh, Jackie Koon Lun Wong, Juo-Jung Hung, Massimo Brandolini, Sha-Ting Lin, Xi Chen, Yen Ding, Yen-Jen Ko, Young Shin, Ada Hing T. Hung, Binning Chen, Cynthia Dang, Deepak Lakshminarasimhan, Iris Hong Liu, Jerry Lin, Kowen Lai, Larry Wassermann, Ayaskant Shrivastava, Chi-Ming Hsiao, Chun-Sheng Huang, Jianlong Chen, Lakshminarasimhan Krishnan, Ning-Yi Wang, Pin-En Su, Tianwei Li, Wei-Ta Shih, Yau-Cheng Yang, Peter Cangiane, Randall Perlow, William Ngai, Hung Sen Huang, James Y. C. Chang, Xicheng Jiang, Ardie G. Venes, Ramon Gomez
2013 J jnl
A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique.
IEEE J. Solid State Circuits
Hyung Seok Kim, Carlos Ornelas, Kailash Chandrashekar, Dan Shi, Pin-En Su, Paolo Madoglio, Yee William Li, Ashoke Ravi
2012 — conf
A digital fractional-N PLL with a 3mW 0.004mm
ESSCIRC
Hyung Seok Kim, Carlos Ornelas, Kailash Chandrashekar, Pin-En Su, Paolo Madoglio, Yee William Li, Ashoke Ravi
2011 J jnl
A 2.4 GHz Wideband Open-Loop GFSK Transmitter With Phase Quantization Noise Cancellation.
IEEE J. Solid State Circuits
Pin-En Su, Sudhakar Pamarti
2011 J jnl
Open-Loop Wide-Bandwidth Phase Modulation Techniques.
J. Electr. Comput. Eng.
Nitin Nidhi, Pin-En Su, Sudhakar Pamarti
2010 J jnl
A 3 , ˟, 3.8 Gb/s Four-Wire High Speed I/O Link Based on CDMA-Like Crosstalk Cancellation.
IEEE J. Solid State Circuits
Tzu-Chien Hsueh, Pin-En Su, Sudhakar Pamarti
2010 J jnl
Mismatch Shaping Techniques to Linearize Charge Pump Errors in Fractional-N PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pin-En Su, Sudhakar Pamarti
2009 — conf
A 3×3.8Gb/s four-wire high speed I/O link based on CDMA-like crosstalk cancellation.
CICC
Tzu-Chien Hsueh, Pin-En Su, Sudhakar Pamarti
2009 J jnl
Fractional-N Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial.
IEEE Trans. Circuits Syst. II Express Briefs
Pin-En Su, Sudhakar Pamarti