Pilar Parra Fernández

13 papers C 2Journal 3Unranked 8

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A Lightweight AES Peripheral for RISC-V Cores and IoT Applications. DCIS Carlos Fernández-García, Carmen Baena Oliva, Pilar Parra Fernández, Carlos Jesús Jiménez-Fernández
2020	J	`jnl`	An Academic Approach to FPGA Design Based on a Distance Meter Circuit. Rev. Iberoam. de Tecnol. del Aprendiz. Carlos Jesús Jiménez-Fernández, Carmen Baena Oliva, Pilar Parra Fernández, Francisco Eugenio Potestad-Ordóñez, Manuel Valencia-Barrero
2020	J	`jnl`	Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA. Sensors Francisco Eugenio Potestad-Ordóñez, Manuel Valencia-Barrero, Carmen Baena Oliva, Pilar Parra Fernández, Carlos Jesús Jiménez-Fernández
2018	—	`conf`	Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher. DCIS Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Carmen Baena Oliva, Pilar Parra Fernández, Manuel Valencia-Barrero
2010	C	`conf`	Optimization of clock-gating structures for low-leakage high-performance applications. ISCAS Javier Castro-Ramirez, Pilar Parra Fernández, Antonio J. Acosta
2009	—	`conf`	Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. PATMOS Javier Castro-Ramirez, Pilar Parra Fernández, Antonio J. Acosta
2007	—	`conf`	A switching noise vision of the optimization techniques for low-power synthesis. ECCTD Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta
2007	C	`conf`	Asymmetric clock driver for improved power and noise performances. ISCAS Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta
2006	—	`conf`	Optimization of Master-Slave Flip-Flops for High-Performance Applications. PATMOS Raúl Jiménez, Pilar Parra Fernández, Javier Castro-Ramirez, Manuel Sanchez-Raya, Antonio J. Acosta
2005	J	`jnl`	Selective Clock-Gating for Low-Power Synchronous Counters. J. Low Power Electron. Pilar Parra Fernández, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia-Barrero
2003	—	`conf`	A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application. PATMOS Raúl Jiménez, Pilar Parra Fernández, Pedro Sanmartín, Antonio J. Acosta
2002	—	`conf`	A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches. PATMOS Raúl Jiménez, Pilar Parra Fernández, Pedro Sanmartín, Antonio J. Acosta
2002	—	`conf`	Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. PATMOS Pilar Parra Fernández, Antonio J. Acosta, Manuel Valencia-Barrero