Pil-Ho Lee

14 papers C 1Journal 10Unranked 3
YearRankTypeTitle / Venue / Authors
2025 J jnl
Strategic design and simulation of interfaces for enhanced joint performance in metal-polymer hybrid structures.
J. Comput. Des. Eng.
Seong Je Park, Joon Phil Choi, Pil-Ho Lee, Seung Ki Moon
2022 — conf
A Fast Lock All-Digital Programmable N/M-ratio MDLL Frequency Multiplier Using a Variable Resolution TDC.
ICEIC
Chaeyoung Jang, Pil-Ho Lee, Sang-jae Rhee, Ki-hwan Choi, Jongsun Kim
2021 — conf
A 7.68 GHz Fast-Lock Low-Jitter Digital MDLL.
ISOCC
Junghoon Jin, SeungJun Kim, Sunguk Choi, Pil-Ho Lee, Sang-jae Rhee, Ki-hwan Choi, Jongsun Kim
2020 J jnl
A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization.
IEEE Trans. Circuits Syst.
Pil-Ho Lee, Young-Chan Jang
2019 J jnl
A 20-Gb/s Receiver Bridge Chip With Auto-Skew Calibration for MIPI D-PHY Interface.
IEEE Trans. Consumer Electron.
Pil-Ho Lee, Young-Chan Jang
2019 J jnl
A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Pil-Ho Lee, Young-Chan Jang
2017 C conf
0.5 kHz-32 MHz digital fractional-N frequency synthesizer with burst-frequency switch.
ISCAS
Seung-Hun Shin, Pil-Ho Lee, Jin-Woo Park, Yu-Jeong Hwang, Young-Chan Jang
2017 J jnl
A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display.
IEICE Trans. Electron.
Ho-Seong Kim, Pil-Ho Lee, Jin-Wook Han, Seung-Hun Shin, Seung-Wuk Baek, Doo-Ill Park, Yongkyu Seo, Young-Chan Jang
2017 J jnl
A 10-Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2.
IEEE Trans. Consumer Electron.
Pil-Ho Lee, Han-Yeol Lee, Yeong-Woong Kim, Han-Young Hong, Young-Chan Jang
2017 — conf
A clock recovery for 2.56 GSymbol/s MIPI C-PHY receiver.
ISOCC
Jin-Wook Han, Pil-Ho Lee, Yeong-Woong Kim, Sang-Dong Kim, Jin-Woo Park, Young-Chan Jang
2017 J jnl
An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock.
IEEE Trans. Very Large Scale Integr. Syst.
Pil-Ho Lee, Han-Yeol Lee, Hyun Bae Lee, Young-Chan Jang
2016 J jnl
A 10-bit 20-MS/s Asynchronous SAR ADC with Meta-Stability Detector Using Replica Comparators.
IEICE Trans. Electron.
Sang-Min Park, Yeon-Ho Jeong, Yu-Jeong Hwang, Pil-Ho Lee, Yeong-Woong Kim, Jisu Son, Han-Yeol Lee, Young-Chan Jang
2016 J jnl
An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis.
IEICE Trans. Electron.
Pil-Ho Lee, Yu-Jeong Hwang, Han-Yeol Lee, Hyun Bae Lee, Young-Chan Jang
2014 J jnl
A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle.
IEICE Trans. Electron.
Pil-Ho Lee, Hyun Bae Lee, Young-Chan Jang