Piet Wambacq - RankMe

205 papers A* 3A 11B 2C 4Journal 70Unranked 114

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Inter-patient ECG Arrhythmia Classification with LGNs and LUTNs. CoRR Wout Mommen, Lars Keuninckx, Paul Detterer, Achiel Colpaert, Piet Wambacq
2025	J	`jnl`	A Compact Current-Reusing 6-mW 66-92 GHz Frequency Quadrupler With 5% Peak Power Added Efficiency and >36 dBc Harmonic Rejection in 22-nm FDSOI CMOS. IEEE Solid State Circuits Lett. Shankkar Balasubramanian, Kristof Vaesen, Piet Wambacq, Carsten Wulff
2025	J	`jnl`	A Method for Optimizing Connections in Differentiable Logic Gate Networks. CoRR Wout Mommen, Lars Keuninckx, Matthias Hartmann, Piet Wambacq
2025	J	`jnl`	A Scalable mK DC Demultiplexer With Extremely Low OFF-Leakage CMOS Switches for Biasing of Spin Qubits. IEEE Solid State Circuits Lett. Alican Çaglar, Imri Fattal, Clement Godfrin, Roy Li, Steven Van Winckel, Kristiaan De Greve, Piet Wambacq, Jan Craninckx
2025	—	`conf`	Noise Analysis of Constant-Slope Voltage-to-Time Converters. PRIME Mattia Gerardi, Jorge-Luis Lagos, Piet Wambacq, Jan Craninckx
2025	—	`conf`	Photonics-enabled Code-Division Multiplexing FMCW Distributed Radar. OFC Chang-Shao Shen, Nishant Singh, Anirudh Kankuppe, Kristof Vaesen, Piet Wambacq, Guy Torfs
2024	—	`conf`	A D-band Power-Combined Stacked Common-Base Power Amplifier Achieving 20.9 dBm Psat and 24.3 % PAE in a 250-nm InP HBT Technology. BCICTS Arno Hemelhof, SeHoon Park, Yang Zhang, Mark Ingels, Giuseppe Gramegna, Kristof Vaesen, Dongyang Yan, Piet Wambacq
2024	B	`conf`	Resource-Efficient Gesture Recognition Using Low-Resolution Thermal Camera via Spiking Neural Networks and Sparse Segmentation. FG Ali Safa, Wout Mommen, Piet Wambacq, Lars Keuninckx
2024	—	`conf`	Toward 0 V ESD Protection in 2.5D/3D Advanced Bonding Technology. VLSI Technology and Circuits S.-H. Lin, Marko Simicic, N. Pantano, S.-H. Chen, Geert Van der Plas, Eric Beyne, Piet Wambacq
2023	—	`conf`	A 0.13μm GaAs HEMT Reconfigurable Balance-to-Doherty Stacked Power Amplifier for 5G mm-wave Applications. PRIME Dongyang Yan, Yang Zhang, Mark Ingels, Piet Wambacq
2023	—	`conf`	A 13-16 GHz Low-Noise Oscillator with Enhanced Tank Energy in 22-nm FDSOI. ESSCIRC Sriram Balamurali, Giovanni Mangraviti, Zhiwei Zhong, Piet Wambacq, Jan Craninckx
2023	—	`conf`	A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL. ISSCC Pratap Tumkur Renukaswamy, Kristof Vaesen, Nereo Markulic, Veerle Derudder, Dae-Woong Park, Piet Wambacq, Jan Craninckx
2023	—	`conf`	A 33 dBm, >30% PAE GaN Power Amplifier Based on a Sub-Quarter-Wavelength Balun for 5G Applications. BCICTS Dongyang Yan, Yang Zhang, Dries Peumans, Mark Ingels, Piet Wambacq
2023	—	`conf`	A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS. ESSCIRC Lucas Moura Santana, Ewout Martens, Jorge Lagos, Piet Wambacq, Jan Craninckx
2023	—	`conf`	A Compact K-band, Asymmetric Coupler-based, Switchless Transmit-Receive Front-End in 0.15μm GaN-on-SiC Technology. ESSCIRC Dongyang Yan, SeHoon Park, Yang Zhang, Mark Ingels, Piet Wambacq
2023	—	`conf`	A Composite AlGaN/cGaN Back Barrier for mm-Wave GaN-on-Si HEMTs. ESSDERC Rana Y. El Kashlan, Hao Yu, Ahmad Khaled, Sachin Yadav, Uthayasankaran Peralagu, AliReza Alian, Nadine Collaert, Piet Wambacq, Bertrand Parvais
2023	J	`jnl`	Design and Analysis of a 4.2 mW 4 K 6-8 GHz CMOS LNA for Superconducting Qubit Readout. IEEE J. Solid State Circuits Alican Çaglar, Steven Van Winckel, Steven Brebels, Piet Wambacq, Jan Craninckx
2023	J	`jnl`	Design of a 10.56-Gb/s 64-QAM Polar Transmitter at 60 GHz in 28-nm CMOS. IEEE J. Solid State Circuits Johan Nguyen, Khaled Khalaf, Xinyan Tang, Steven Brebels, Kristof Vaesen, Mithlesh Shrivas, Piet Wambacq
2023	—	`conf`	Foreword: Building on 70 Years of Innovation in Solid-State Circuit Design. ISSCC Piet Wambacq
2023	—	`conf`	The Promise of 2-D Materials for Scaled Digital and Analog Applications. ISSCC Devin Verreck, Piet Wambacq, Maarten Van De Put, Zubair Ahmed, Quentin Smets, Aryan Afzalian, Rutger Duflou, Xiangyu Wu, Gioele Mirabelli, Rongmei Chen, Inge Asselberghs, Gouri Sankar Kar
2022	—	`conf`	A 28nm 6.5-8.1GHz 1.16mW/qubit Cryo-CMOS System-an-Chip for Superconducting Qubit Readout. ESSCIRC Steven Van Winckel, Alican Çaglar, Benjamin Gys, Steven Brebels, Anton Potocnik, Bertrand Parvais, Piet Wambacq, Jan Craninckx
2022	J	`jnl`	A 67-mW D-Band FMCW I/Q Radar Receiver With an N-Path Spillover Notch Filter in 28-nm CMOS. IEEE J. Solid State Circuits Anirudh Kankuppe, SeHoon Park, Kristof Vaesen, Dae-Woong Park, Barend van Liempd, Siddhartha Sinha, Piet Wambacq, Jan Craninckx
2022	J	`jnl`	A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS. IEEE J. Solid State Circuits Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
2022	J	`jnl`	A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS. IEEE J. Solid State Circuits SeHoon Park, Dae-Woong Park, Kristof Vaesen, Anirudh Kankuppe, Siddhartha Sinha, Barend van Liempd, Piet Wambacq, Jan Craninckx
2022	J	`jnl`	Design and Analysis of 55-63-GHz Fundamental Quad-Core VCO With NMOS-Only Stacked Oscillator in 28-nm CMOS. IEEE J. Solid State Circuits Sriram Balamurali, Giovanni Mangraviti, Cheng-Hsueh Tsai, Piet Wambacq, Jan Craninckx
2022	J	`jnl`	Design and Analysis of a 140-GHz T/R Front-End Module in 22-nm FD-SOI CMOS. IEEE J. Solid State Circuits Xinyan Tang, Johan Nguyen, Giovanni Mangraviti, Zhiwei Zong, Piet Wambacq
2022	—	`conf`	III-V HBTs on 300 mm Si substrates using merged nano-ridges and its application in the study of impact of defects on DC and RF performance. ESSDERC Abhitosh Vais, Sachin Yadav, Yves Mols, Bjorn Vermeersch, Komal Vondkar Kodandarama, Marina Baryshnikova, G. Mannaert, R. Alcotte, Geert Boccardi, Piet Wambacq, Bertrand Parvais, R. Langer, Bernardette Kunert, Nadine Collaert
2021	—	`conf`	26.4 A Reflection-Coefficient Sensor for 28GHz Beamforming Transmitters in 22nm FD-SOI CMOS. ISSCC Yang Zhang, Giovanni Mangraviti, Johan Nguyen, Zhiwei Zong, Piet Wambacq
2021	J	`jnl`	A 28-nm-CMOS Based 145-GHz FMCW Radar: System, Circuits, and Characterization. IEEE J. Solid State Circuits Akshay Visweswaran, Kristof Vaesen, Miguel Glassee, Anirudh Kankuppe, Siddhartha Sinha, Claude Desset, Thomas Gielen, André Bourdoux, Piet Wambacq
2021	—	`conf`	A 4.2mW 4K 6-8GHz CMOS LNA for Superconducting Qubit Readout. A-SSCC Alican Çaglar, Steven Van Winckel, Steven Brebels, Piet Wambacq, Jan Craninckx
2021	—	`conf`	A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC. ESSCIRC Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
2021	—	`conf`	A 55-63 GHz fundamental Quad-Core VCO with NMOS-only stacked oscillator in 28 nm CMOS. ESSCIRC Sriram Balamurali, Giovanni Mangraviti, Cheng-Hsueh Tsai, Piet Wambacq, Jan Craninckx
2021	—	`conf`	A 67mW D-band FMCW I/Q Radar Receiver with an N-path Spillover Notch Filter in 28nm CMOS. ESSCIRC Anirudh Kankuppe, SeHoon Park, Kristof Vaesen, Dae-Woong Park, Barend van Liempd, Piet Wambacq, Jan Craninckx
2021	J	`jnl`	A Low-Power Reflection-Coefficient Sensor for 28-GHz Beamforming Transmitters in 22-nm FD-SOI CMOS. IEEE J. Solid State Circuits Yang Zhang, Giovanni Mangraviti, Johan Nguyen, Zhiwei Zong, Kamil Yavuz Kapusuz, Sam Lemey, Hendrik Rogier, Giuseppe Gramegna, Piet Wambacq
2021	C	`conf`	Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. ISCAS Pratap Tumkur Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx
2020	—	`conf`	17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth. ISSCC Pratap Tumkur Renukaswamy, Nereo Markulic, SeHoon Park, Anirudh Kankuppe, Qixian Shi, Piet Wambacq, Jan Craninckx
2020	—	`conf`	A 1 IEEE SENSORS Toshio Yasue, Fortunato Frazzica, Annachiara Spagnolo, David San Segundo Bello, Maarten De Bock, Piet Wambacq, Jan Craninckx
2020	J	`jnl`	A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth. IEEE J. Solid State Circuits Pratap Tumkur Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx
2020	—	`conf`	A 247 and 272 GHz Two-Stage Regenerative Amplifiers in 65 nm CMOS with 18 and 15 dB Gain Based on Double-Gmax Gain Boosting Technique. VLSI Circuits Dae-Woong Park, Dzuhri Radityo Utomo, Jong-Phil Hong, Kristof Vaesen, Piet Wambacq, Sang-Gug Lee
2020	—	`conf`	A 28GHz Two-Way Current Combining Stacked-FET Power Amplifier in 22nm FD-SOI. CICC Zhiwei Zong, Xinyan Tang, Johan Nguyen, Khaled Khalaf, Giovanni Mangraviti, Yao Liu, Piet Wambacq
2020	B	`conf`	A flexible power model for mm-wave and THz high-throughput communication systems. PIMRC Claude Desset, Piet Wambacq, Yang Zhang, Mark Ingels, André Bourdoux
2020	J	`jnl`	Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication. IEEE J. Solid State Circuits Cheng-Hsueh Tsai, Zhiwei Zong, Federico Pepe, Giovanni Mangraviti, Jan Craninckx, Piet Wambacq
2020	J	`jnl`	Design of D-Band Transformer-Based Gain-Boosting Class-AB Power Amplifiers in Silicon Technologies. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. Xinyan Tang, Johan Nguyen, Alaaeldien Medra, Khaled Khalaf, Akshay Visweswaran, Björn Debaillie, Piet Wambacq
2020	J	`jnl`	Low 1/f IEEE Trans. Circuits Syst. I Fundam. Theory Appl. Zhiwei Zong, Giovanni Mangraviti, Piet Wambacq
2019	J	`jnl`	A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers. IEEE J. Solid State Circuits Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
2019	—	`conf`	A 112-142GHz Power Amplifier with Regenerative Reactive Feedback achieving 17dBm peak Psat at 13% PAE. ESSCIRC Akshay Visweswaran, Bastien Vignon, Xinyan Tang, Steven Brebels, Björn Debaillie, Piet Wambacq
2019	—	`conf`	A 145GHz FMCW-Radar Transceiver in 28nm CMOS. ISSCC Akshay Visweswaran, Kristof Vaesen, Siddhartha Sinha, Ilja Ocket, Miguel Glassee, Claude Desset, André Bourdoux, Piet Wambacq
2019	—	`conf`	A 22-29 GHz Voltage-Biased LC-VCO with Suppressed Flicker Noise over Tuning Range in 22nm FD-SOI. NEWCAS Zhiwei Zong, Giovanni Mangraviti, Piet Wambacq
2019	—	`conf`	A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication With 220-fs RMS Jitter. ESSCIRC Cheng-Hsueh Tsai, Federico Pepe, Giovanni Mangraviti, Zhiwei Zong, Jan Craninckx, Piet Wambacq
2019	J	`jnl`	A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS. IEEE J. Solid State Circuits Nereo Markulic, Pratap Tumkur Renukaswamy, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx
2019	J	`jnl`	A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS. IEEE J. Solid State Circuits Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
2019	—	`conf`	Design of A D-band Transformer-Based Neutralized Class-AB Power Amplifier in Silicon Technologies. NEWCAS Xinyan Tang, Alaaeldien Medra, Johan Nguyen, Khaled Khalaf, Björn Debaillie, Piet Wambacq
2019	—	`conf`	Design of a 28 GHz differential GaAs power amplifier with capacitive neutralization for 5G mmwave applications. NEWCAS Dongyang Yan, Mark Ingels, Giovanni Mangraviti, Yao Liu, Bertrand Parvais, Niamh Waldron, Nadine Collaert, Piet Wambacq
2019	—	`conf`	Millimeter-Wave Transceivers for Wireless Communication, Radar, and Sensing : (Invited Paper). CICC Aritra Banerjee, Kristof Vaesen, Akshay Visweswaran, Khaled Khalaf, Qixian Shi, Steven Brebels, Davide Guermandi, Cheng-Hsueh Tsai, Johan Nguyen, Alaa Medra, Yao Liu, Giovanni Mangraviti, Orges Furxhi, Bert Gyselinckx, André Bourdoux, Jan Craninckx, Piet Wambacq
2019	J	`jnl`	Multi-User Hybrid MIMO at 60 GHz Using 16-Antenna Transmitters. IEEE Trans. Circuits Syst. I Regul. Pap. Steve Blandino, Giovanni Mangraviti, Claude Desset, André Bourdoux, Piet Wambacq, Sofie Pollin
2019	—	`conf`	Systematic Design of On-Chip Matching Networks for D-band Circuits. NEWCAS Johan Nguyen, Xinyan Tang, Khaled Khalaf, Björn Debaillie, Piet Wambacq
2018	—	`conf`	A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers. CICC Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
2018	—	`conf`	A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS. VLSI Circuits Nereo Markulic, Pratap Renukaswarny, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx
2018	J	`jnl`	A 60-GHz 8-Way Phased-Array Front-End With T/R Switching and Calibration-Free Beamsteering in 28-nm CMOS. IEEE J. Solid State Circuits Khaled Khalaf, Kristof Vaesen, Steven Brebels, Giovanni Mangraviti, Michael Libois, Charlotte Soens, Wim Van Thillo, Piet Wambacq
2018	J	`jnl`	Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification. Sensors Lin-Kun Wu, David San Segundo Bello, Philippe Coppejans, Jan Craninckx, Andreas Süss, Maarten Rosmeulen, Piet Wambacq, Jonathan Borremans
2018	—	`conf`	Scaling CMOS beyond Si FinFET: an analog/RF perspective. ESSDERC Bertrand Parvais, Geert Hellings, Marko Simicic, Pieter Weckx, Jérôme Mitard, Doyoung Jang, V. Deshpande, B. van Liempc, Anabela Veloso, A. Vandooren, Niamh Waldron, Piet Wambacq, Nadine Collaert, Diederik Verkest
2018	—	`conf`	Session 15 overview: RF PLLs: RF subcommittee. ISSCC Jiayoon Ru, Jaehyouk Choi, Piet Wambacq
2018	—	`conf`	Session 23 overview: LO generation: RF subcommittee. ISSCC Hyunchol Shin, Andrea Bevilacqua, Piet Wambacq
2018	—	`conf`	Session 26 overview: RF techniques for communication and sensing: RF subcommittee. ISSCC Giuseppe Gramegna, Hua Wang, Piet Wambacq
2017	—	`conf`	A 54-64.8 GHz subharmonically injection-locked frequency synthesizer with transmitter EVM between -26.5 dB and -28.8 dB in 28 nm CMOS. ESSCIRC Cheng-Hsueh Tsai, Giovanni Mangraviti, Qixian Shi, Khaled Khalaf, André Bourdoux, Piet Wambacq
2017	—	`conf`	A 60GHz 8-way phased array front-end with TR switching and calibration-free beamsteering in 28nm CMOS. ESSCIRC Khaled Khalaf, Kristof Vaesen, Steven Brebels, Giovanni Mangraviti, Michael Libois, Charlotte Soens, Piet Wambacq
2017	J	`jnl`	A 79-GHz 2 × 2 MIMO PMCW Radar SoC in 28-nm CMOS. IEEE J. Solid State Circuits Davide Guermandi, Qixian Shi, Andy Dewilde, Veerle Derudder, Ubaid Ahmad, Annachiara Spagnolo, Ilja Ocket, André Bourdoux, Piet Wambacq, Jan Craninckx, Wim Van Thillo
2017	—	`conf`	An up to 36Gbps analog baseband equalizer and demodulator for mm-wave wireless communication in 28nm CMOS. CICC Oscar Elisio Mattia, Davide Guermandi, Guy Torfs, Piet Wambacq
2017	—	`conf`	Session 17 overview: TX and RX building blocks. ISSCC Brian P. Ginsburg, Payam Heydari, Piet Wambacq
2017	—	`conf`	Session 19 overview: Frequency generation. ISSCC Andrea Mazzanti, Xiang Gao, Piet Wambacq
2017	—	`conf`	Session 2 overview: Power amplifiers. ISSCC Kohei Onizuka, Abbas Komijani, Piet Wambacq
2017	J	`jnl`	Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond. IEEE Trans. Very Large Scale Integr. Syst. Trong Huynh Bao, Julien Ryckaert, Zsolt Tokei, Abdelkarim Mercha, Diederik Verkest, Aaron Voon-Yew Thean, Piet Wambacq
2016	—	`conf`	13.5 A 4-antenna-path beamforming transceiver for 60GHz multi-Gb/s communication in 28nm CMOS. ISSCC Giovanni Mangraviti, Khaled Khalaf, Qixian Shi, Kristof Vaesen, Davide Guermandi, Vito Giannini, Steven Brebels, Fortunato Frazzica, André Bourdoux, Charlotte Soens, Wim Van Thillo, Piet Wambacq
2016	—	`conf`	13.7 A 0.22mm2 CMOS resistive charge-based direct-launch digital transmitter with -159dBc/Hz out-of-band noise. ISSCC Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx
2016	—	`conf`	20.8 A dual-frequency 0.7-to-1GHz balance network for electrical balance duplexers. ISSCC Benjamin P. Hershberg, Barend van Liempd, Xiaoqiang Zhang, Piet Wambacq, Jan Craninckx
2016	—	`conf`	9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL. ISSCC Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
2016	J	`jnl`	A 150 kHz-80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS. IEEE J. Solid State Circuits Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx
2016	—	`conf`	A 28 nm CMOS 7.04 Gsps polar digital front-end processor for 60 GHz transmitter. A-SSCC Yanxiang Huang, Chunshu Li, Khaled Khalaf, André Bourdoux, Julien Verschueren, Qixian Shi, Piet Wambacq, Sofie Pollin, Wim Dehaene, Liesbet Van der Perre
2016	—	`conf`	A 79GHz 2×2 MIMO PMCW radar SoC in 28nm CMOS. A-SSCC Davide Guermandi, Qixian Shi, Andy Dewilde, Veerle Derudder, Ubaid Ahmad, Annachiara Spagnolo, André Bourdoux, Piet Wambacq, Wim Van Thillo
2016	J	`jnl`	A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation. IEEE J. Solid State Circuits Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
2016	—	`conf`	A Fractional-n subsampling PLL based on a digital-to-time converter. MIPRO Nereo Markulic, Kuba Raczkowski, Piet Wambacq, Jan Craninckx
2016	J	`jnl`	An 80 GHz Low-Noise Amplifier Resilient to the TX Spillover in Phase-Modulated Continuous-Wave Radars. IEEE J. Solid State Circuits Alaa Medra, Davide Guermandi, Kristof Vaesen, Steven Brebels, André Bourdoux, Wim Van Thillo, Piet Wambacq, Vito Giannini
2016	J	`jnl`	Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication. IEEE J. Solid State Circuits Khaled Khalaf, Vojkan Vidojkovic, Kristof Vaesen, Michael Libois, Giovanni Mangraviti, Viki Szortyka, Chunshu Li, Bob Verbruggen, Mark Ingels, André Bourdoux, Charlotte Soens, Wim Van Thillo, John R. Long, Piet Wambacq
2015	—	`conf`	19.7 A 79GHz binary phase-modulated continuous-wave radar transceiver with TX-to-RX spillover cancellation in 28nm CMOS. ISSCC Davide Guermandi, Qixian Shi, Alaa Medra, Tomohiro Murata, Wim Van Thillo, André Bourdoux, Piet Wambacq, Vito Giannini
2015	—	`conf`	9.3 A transmitter with 10b 128MS/S incremental-charge-based DAC achieving -155dBc/Hz out-of-band noise. ISSCC Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx
2015	—	`conf`	A 0.7-1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection. ESSCIRC Barend van Liempd, Saneaki Ariumi, Ewout Martens, Shih-Hung Chen, Piet Wambacq, Jan Craninckx
2015	—	`conf`	A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5 ESSCIRC Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx
2015	J	`jnl`	A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS. IEEE J. Solid State Circuits Viki Szortyka, Qixian Shi, Kuba Raczkowski, Bertrand Parvais, Maarten Kuijk, Piet Wambacq
2015	—	`conf`	A 6x-oversampling 10GS/s 60GHz polar transmitter with 15.3% average PA efficiency in 40nm CMOS. ESSCIRC Khaled Khalaf, Vojkan Vidojkovic, John R. Long, Piet Wambacq
2015	J	`jnl`	A Wideband Beamforming Lowpass Filter for 60 GHz Phased-Array Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. Viki Szortyka, Kuba Raczkowski, Maarten Kuijk, Piet Wambacq
2015	—	`conf`	A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS. A-SSCC Bertrand Parvais, Piet Wambacq, Abdelkarim Mercha, Diederik Verkest, Aaron Thean, Ken Sawada, Kazuki Nomoto, Tetsuya Oishi, Hiroaki Ammo
2015	J	`jnl`	An Incremental-Charge-Based Digital Transmitter With Built-in Filtering. IEEE J. Solid State Circuits Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx
2015	—	`conf`	An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power. ESSCIRC Barend van Liempd, Benjamin P. Hershberg, Björn Debaillie, Piet Wambacq, Jan Craninckx
2015	J	`jnl`	Correction to "A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range". IEEE J. Solid State Circuits Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx
2015	—	`book`	Data Transmission at Millimeter Waves - Exploiting the 60 GHz Band on Silicon Khaled Khalaf, Vojkan Vidojkovic, Piet Wambacq, John R. Long
2015	—	`conf`	Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM. ICICDT Trong Huynh Bao, Sushil Sakhare, Julien Ryckaert, Dmitry Yakimets, Abdelkarim Mercha, Diederik Verkest, Aaron Voon-Yew Thean, Piet Wambacq
2015	—	`conf`	F5: Advanced RF CMOS transmitter techniques. ISSCC Piet Wambacq, Stefano Pellerano, Sven Mattisson, Shouhei Kousai, Ali Afsahi, Taizo Yamawaki
2015	—	`conf`	Flicker noise upconversion mechanisms in K-band CMOS VCOs. A-SSCC Qixian Shi, Davide Guermandi, Jan Craninckx, Piet Wambacq
2015	—	`conf`	High-speed analog-to-digital converters in downscaled CMOS. ICICDT Annachiara Spagnolo, Bob Verbruggen, Stefano D'Amico, Piet Wambacq
2015	—	`conf`	Modeling FinFET metal gate stack resistance for 14nm node and beyond. ICICDT Kenichi Miyaguchi, Bertrand Parvais, Lars-Åke Ragnarsson, Piet Wambacq, Praveen Raghavan, Abdelkarim Mercha, Anda Mocuta, Diederik Verkest, Aaron Thean
2015	J	`jnl`	Opportunities and Challenges of Digital Signal Processing in Deeply Technology-Scaled Transceivers. J. Signal Process. Syst. Chunshu Li, Min Li, Khaled Khalaf, André Bourdoux, Marian Verhelst, Mark Ingels, Piet Wambacq, Jan Craninckx, Liesbet Van der Perre, Sofie Pollin
2014	—	`conf`	14.2 A 79GHz phase-modulated 4GHz-BW CW radar TX in 28nm CMOS. ISSCC Vito Giannini, Davide Guermandi, Qixian Shi, Kristof Vaesen, Bertrand Parvais, Wim Van Thillo, André Bourdoux, Charlotte Soens, Jan Craninckx, Piet Wambacq
2014	—	`conf`	21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS. ISSCC Viki Szortyka, Qixian Shi, Kuba Raczkowski, Bertrand Parvais, Maarten Kuijk, Piet Wambacq
2014	—	`conf`	A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS. ESSCIRC Nereo Markulic, Kuba Raczkowski, Piet Wambacq, Jan Craninckx
2014	J	`jnl`	A 4.1-mW 3.5-GS/s 6-Bit Time-Interleaved ADC in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Annachiara Spagnolo, Bob Verbruggen, Piet Wambacq, Stefano D'Amico
2014	—	`conf`	A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS. ESSCIRC Annachiara Spagnolo, Bob Verbruggen, Stefano D'Amico, Piet Wambacq
2014	J	`jnl`	A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range. IEEE J. Solid State Circuits Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx
2014	J	`jnl`	A 79 GHz Phase-Modulated 4 GHz-BW CW Radar Transmitter in 28 nm CMOS. IEEE J. Solid State Circuits Vito Giannini, Davide Guermandi, Qixian Shi, Alaa Medra, Wim Van Thillo, André Bourdoux, Piet Wambacq
2014	—	`conf`	A 79GHz variable gain low-noise amplifier and power amplifier in 28nm CMOS operating up to 125°C. ESSCIRC Alaa Medra, Vito Giannini, Davide Guermandi, Piet Wambacq
2014	—	`conf`	A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC. ESSCIRC Badr Malki, Bob Verbruggen, Piet Wambacq, Kazuaki Deguchi, Masao Iriguchi, Jan Craninckx
2014	—	`conf`	Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. ESSDERC Trong Huynh Bao, Dmitry Yakimets, Julien Ryckaert, Ivan Ciofi, Rogier Baert, Anabela Veloso, Jürgen Bömmels, Nadine Collaert, Philippe Roussel, S. Demuynck, Praveen Raghavan, Abdelkarim Mercha, Zsolt Tokei, Diederik Verkest, Aaron Thean, Piet Wambacq
2014	—	`conf`	Design Technology co-optimization for N10. CICC Julien Ryckaert, Praveen Raghavan, Rogier Baert, Marie Garcia Bardon, Mircea Dusa, Arindam Mallik, Sushil Sakhare, Boris Vandewalle, Piet Wambacq, Bharani Chava, Kris Croes, Morin Dehan, Doyoung Jang, Philippe Leray, Tsung-Te Liu, Kenichi Miyaguchi, Bertrand Parvais, Pieter Schuddinck, Philippe Weemaes, Abdelkarim Mercha, Jürgen Bömmels, Naoto Horiguchi, Greg McIntyre, Aaron Thean, Zsolt Tökei, Shaunee Cheng, Diederik Verkest, An Steegen
2013	—	`conf`	A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication. ISSCC Vojkan Vidojkovic, Viki Szortyka, Khaled Khalaf, Giovanni Mangraviti, Steven Brebels, Wim Van Thillo, Kristof Vaesen, Bertrand Parvais, Vadim Issakov, Mike Libois, Michiaki Matsuo, John R. Long, Charlotte Soens, Piet Wambacq
2013	—	`conf`	CMOS low-power transceivers for 60GHz multi Gbit/s communications. CICC Vojkan Vidojkovic, Viki Szortyka, Khaled Khalaf, Giovanni Mangraviti, Bertrand Parvais, Kristof Vaesen, Steven Brebels, Annachiara Spagnolo, Michael Libois, John R. Long, Kuba Raczkowski, Praveen Raghavan, André Bourdoux, Min Li, Charlotte Soens, Vito Giannini, Piet Wambacq
2013	—	`conf`	F6: Mixed-signal/RF design and modeling in next-generation CMOS. ISSCC Boris Murmann, Jafar Savoj, Piet Wambacq, Jieh-Tsorng Wu
2013	—	`conf`	Signal processing challenges for emerging digital intensive and digitally assisted transceivers with deeply scaled technology (Invited). SiPS Min Li, Khaled Khalaf, Chunshu Li, Vojkan Vidojkovic, Mark Ingels, André Bourdoux, Piet Wambacq, Jan Craninckx, Liesbet Van der Perre
2012	—	`conf`	A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range. ISSCC Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx
2012	—	`conf`	A CMOS IQ Digital Doherty Transmitter using modulated tuning capacitors. ESSCIRC Wagdy M. Gaber, Piet Wambacq, Jan Craninckx, Mark Ingels
2012	—	`conf`	A low-power 57-to-66GHz transceiver in 40nm LP CMOS with -17dB EVM at 7Gb/s. ISSCC Vojkan Vidojkovic, Giovanni Mangraviti, Khaled Khalaf, Viki Szortyka, Kristof Vaesen, Wim Van Thillo, Bertrand Parvais, Mike Libois, Steven Thijs, John R. Long, Charlotte Soens, Piet Wambacq
2011	—	`conf`	A CMOS IQ direct digital RF modulator with embedded RF FIR-based quantization noise filter. ESSCIRC Wagdy M. Gaber, Piet Wambacq, Jan Craninckx, Mark Ingels
2010	J	`jnl`	A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS. IEEE J. Solid State Circuits Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas
2010	—	`conf`	A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS. ISSCC Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas
2010	—	`conf`	A 40 nm LP CMOS PLL for high-speed mm-wave communication. ESSCIRC Bertrand Parvais, Karen Scheir, Vojkan Vidojkovic, R. Vandebriel, Gerd Vandersteen, Charlotte Soens, Piet Wambacq
2010	—	`conf`	A fifth-order 880MHz/1.76GHz active lowpass filter for 60GHz communications in 40nm digital CMOS. ESSCIRC Piet Wambacq, Vito Giannini, Karen Scheir, Wim Van Thillo, Yves Rolain
2010	—	`conf`	A wideband beamformer for a phased-array 60GHz receiver in 40nm digital CMOS. ISSCC Kuba Raczkowski, Walter De Raedt, Bart Nauwelaers, Piet Wambacq
2009	—	`conf`	50-to-67GHz ESD-protected power amplifiers in digital 45nm LP CMOS. ISSCC Kuba Raczkowski, Steven Thijs, Walter De Raedt, Bart Nauwelaers, Piet Wambacq
2009	J	`jnl`	A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS. IEEE J. Solid State Circuits Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas
2009	—	`conf`	A 57-to-66GHz quadrature PLL in 45nm digital CMOS. ISSCC Karen Scheir, Gerd Vandersteen, Yves Rolain, Piet Wambacq
2009	J	`jnl`	A Fully Integrated 7.3 kV HBM ESD-Protected Transformer-Based 4.5-6 GHz CMOS LNA. IEEE J. Solid State Circuits Jonathan Borremans, Steven Thijs, Piet Wambacq, Yves Rolain, Dimitri Linten, Maarten Kuijk
2009	J	`jnl`	A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS. IEEE J. Solid State Circuits Jonathan Borremans, Julien Ryckaert, Claude Desset, Maarten Kuijk, Piet Wambacq, Jan Craninckx
2009	—	`conf`	A digitally controlled compact 57-to-66GHz front-end in 45nm digital CMOS. ISSCC Jonathan Borremans, Kuba Raczkowski, Piet Wambacq
2009	J	`jnl`	A plug-and-play wideband RF circuit ESD protection methodology: T-diodes. Microelectron. Reliab. Dimitri Linten, Steven Thijs, Jonathan Borremans, Morin Dehan, David Trémouilles, Mirko Scholz, M. I. Natarajan, Piet Wambacq, Stefaan Decoutere, Guido Groeseneken
2009	—	`conf`	FinFET RF receiver building blocks operating above 10 GHz. ESSCIRC Domagoj Siprak, Piet Wambacq, Bertrand Parvais, Abdelkarim Mercha, Michael Fulde, Jesenka Veledar Kruger, Morin Dehan, Stefaan Decoutere
2009	—	`conf`	Low-cost feedback-enabled LNAs in 45nm CMOS. ESSCIRC Jonathan Borremans, Steven Thijs, Morin Dehan, Abdelkarim Mercha, Piet Wambacq
2008	J	`jnl`	A 100-kHz to 20-MHz Reconfigurable Power-Linearity Optimized G IEEE Trans. Circuits Syst. II Express Briefs Pieter Crombez, Jan Craninckx, Piet Wambacq, Michiel Steyaert
2008	—	`conf`	A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS. ISSCC Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas
2008	—	`conf`	A 400 μW 4.7-to-6.4GHz VCO under an Above-IC Inductor in 45nm CMOS. ISSCC Jonathan Borremans, Piet Wambacq, Maarten Kuijk, Geert Carchon, Stefaan Decoutere
2008	J	`jnl`	A 52 GHz Phased-Array Receiver Front-End in 90 nm Digital CMOS. IEEE J. Solid State Circuits Karen Scheir, Stephane Bronckers, Jonathan Borremans, Piet Wambacq, Yves Rolain
2008	—	`conf`	A 52GHz Phased-Array Receiver Front-End in 90nm Digital CMOS. ISSCC Karen Scheir, Stephane Bronckers, Jonathan Borremans, Piet Wambacq, Yves Rolain
2008	J	`jnl`	A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS. IEEE J. Solid State Circuits Jonathan Borremans, Andrea Bevilacqua, Stephane Bronckers, Morin Dehan, Maarten Kuijk, Piet Wambacq, Jan Craninckx
2008	—	`conf`	A Single-Inductor Dual-Band VCO in a 0.06mm ISSCC Jonathan Borremans, Stephane Bronckers, Piet Wambacq, Maarten Kuijk, Jan Craninckx
2008	—	`conf`	A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS. ESSCIRC Jonathan Borremans, Julien Ryckaert, Piet Wambacq, Maarten Kuijk, Jan Craninckx
2008	—	`conf`	Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies. ISSCC Piet Wambacq, Abdelkarim Mercha, Karen Scheir, Bob Verbruggen, Jonathan Borremans, Vincent De Heyn, Steven Thijs, Dimitri Linten, Geert Van der Plas, Bertrand Parvais, Morin Dehan, Stefaan Decoutere, Charlotte Soens, Nadine Collaert, Malgorzata Jurczak
2008	—	`conf`	Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications. CICC Steven Thijs, Mototsugu Okushima, Jonathan Borremans, Philippe Jansen, Dimitri Linten, Mirko Scholz, Piet Wambacq, Guido Groeseneken
2008	J	`jnl`	Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS. IEEE J. Solid State Circuits Jonathan Borremans, Piet Wambacq, Charlotte Soens, Yves Rolain, Maarten Kuijk
2007	J	`jnl`	A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication. IEEE J. Solid State Circuits Julien Ryckaert, Marian Verhelst, Mustafa Badaroglu, Stefano D'Amico, Vincent De Heyn, Claude Desset, Pierluigi Nuzzo, Bart van Poucke, Piet Wambacq, Andrea Baschirotto, Wim Dehaene, Geert Van der Plas
2007	—	`conf`	A switchable low-area 2.4-and-5 GHz dual-band LNA in digital CMOS. ESSCIRC Jonathan Borremans, Piet Wambacq, Geert Van der Plas, Yves Rolain, Maarten Kuijk
2007	—	`conf`	An ESD-Protected DC-to-6GHz 9.7mW LNA in 90nm Digital CMOS. ISSCC Jonathan Borremans, Piet Wambacq, Dimitri Linten
2007	—	`conf`	Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy. ISSCC Liesbet Van der Perre, Bruno Bougard, Jan Craninckx, Wim Dehaene, Lieven Hollevoet, Murali Jayapala, Pol Marchal, Miguel Miranda, Praveen Raghavan, Thomas Schuster, Piet Wambacq, Francky Catthoor, Peter Vanbekbergen
2007	—	`conf`	FinFET technology for analog and RF circuits. ICECS Bertrand Parvais, Vaidyanathan Subramanian, Abdelkarim Mercha, Morin Dehan, Piet Wambacq, Willy Sansen, Guido Groeseneken, Stefaan Decoutere
2007	—	`conf`	Impact of Sampling Jitter on Mostly-Digital Architectures for UWB Bio-Medical Applications. ICC Andrew Fort, Mike Shuo-Wei Chen, Robert W. Brodersen, Claude Desset, Piet Wambacq, Leo Van Biesen
2007	—	`conf`	Linearity guidelines for gm-C biquad filter design using architecture optimization with Volterra analysis. ECCTD Pieter Crombez, Jan Craninckx, Piet Wambacq, Michiel Steyaert
2007	A	`conf`	Nonlinearity analysis of Analog/RF circuits using combined multisine and volterra analysis. DATE Jonathan Borremans, Ludwig De Locht, Piet Wambacq, Yves Rolain
2007	C	`conf`	Scalable Gate-Level Models for Power and Timing Analysis. ISCAS Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2007	J	`jnl`	Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance CoRR Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay
2007	J	`jnl`	The Potential of FinFETs for Analog and RF Circuit Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Piet Wambacq, Bob Verbruggen, Karen Scheir, Jonathan Borremans, Morin Dehan, Dimitri Linten, Vincent De Heyn, Geert Van der Plas, Abdelkarim Mercha, Bertrand Parvais, Cedric Gustin, Vaidyanathan Subramanian, Nadine Collaert, Malgorzata Jurczak, Stefaan Decoutere
2006	—	`conf`	A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS. ISSCC Julien Ryckaert, Mustafa Badaroglu, Vincent De Heyn, Geert Van der Plas, Pierluigi Nuzzo, Andrea Baschirotto, Stefano D'Amico, Claude Desset, Hans Suys, Michael Libois, Bart van Poucke, Piet Wambacq, Bert Gyselinckx
2006	J	`jnl`	Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling. EURASIP J. Wirel. Commun. Netw. Mustafa Badaroglu, Claude Desset, Julien Ryckaert, Vincent De Heyn, Geert Van der Plas, Piet Wambacq, Bart van Poucke
2006	—	`conf`	Body Area UWB RAKE Receiver Communication. ICC Andrew Fort, Claude Desset, Piet Wambacq, Leo Van Biesen
2006	J	`jnl`	Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2006	J	`jnl`	Evolution of substrate noise generation mechanisms with CMOS technology scaling. IEEE Trans. Circuits Syst. I Regul. Pap. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
2006	J	`jnl`	Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate. IEEE J. Solid State Circuits Charlotte Soens, Geert Van der Plas, Mustafa Badaroglu, Piet Wambacq, Stéphane Donnay, Yves Rolain, Maarten Kuijk
2006	J	`jnl`	SWAN: high-level simulation methodology for digital substrate noise generation. IEEE Trans. Very Large Scale Integr. Syst. Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2006	—	`conf`	Technologies for (sub-) 45nm Analog/RF CMOS - Circuit Design Opportunities and Challenges. CICC Stefaan Decoutere, Piet Wambacq, Vaidy Subramanian, Jonathan Borremans, Abdelkarim Mercha
2006	J	`jnl`	Ultra-wideband channel model for communication around the human body. IEEE J. Sel. Areas Commun. Andrew Fort, Julien Ryckaert, Claude Desset, Philippe De Doncker, Piet Wambacq, Leo Van Biesen
2005	J	`jnl`	A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS. IEEE J. Solid State Circuits Dimitri Linten, Steven Thijs, Mahadeva Iyer Natarajan, Piet Wambacq, Wutthinan Jeamsaksiri, Javier Ramos, Abdelkarim Mercha, Snezana Jenei, Stéphane Donnay, Stefaan Decoutere
2005	J	`jnl`	Digital ground bounce reduction by supply current shaping and clock frequency Modulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2005	J	`jnl`	ESD-RF co-design methodology for the state of the art RF-CMOS blocks. Microelectron. Reliab. Vesselin K. Vassilev, Steven Thijs, P. L. Segura, Piet Wambacq, Paul Leroux, Guido Groeseneken, M. I. Natarajan, Herman E. Maes, Michiel Steyaert
2005	—	`conf`	Low-power low-noise highly ESD robust LNA, and VCO design using above-IC inductors. CICC Dimitri Linten, Xiao Sun, Steven Thijs, M. I. Natarajan, Abdelkarim Mercha, Geert Carchon, Piet Wambacq, Takeshi Nakaie, Stefaan Decoutere
2005	J	`jnl`	Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors. IEEE J. Solid State Circuits Dimitri Linten, Xiao Sun, Geert Carchon, Wutthinan Jeamsaksiri, Abdelkarim Mercha, Javier Ramos, Snezana Jenei, Piet Wambacq, Morin Dehan, Lars Aspemyr, Andries J. Scholten, Stefaan Decoutere, Stéphane Donnay, Walter De Raedt
2005	J	`jnl`	Performance degradation of LC-tank VCOs by impact of digital switching noise in lightly doped substrates. IEEE J. Solid State Circuits Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Maarten Kuijk
2005	A	`conf`	Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. DATE Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay
2005	—	`conf`	Substrate noise immune design of an LC-tank VCO using sensitivity functions. CICC Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay
2005	J	`jnl`	Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation. IEEE Trans. Circuits Syst. I Regul. Pap. Julien Ryckaert, Claude Desset, Andrew Fort, Mustafa Badaroglu, Vincent De Heyn, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Bart van Poucke, Bert Gyselinckx
2004	—	`conf`	A 328 μW 5 GHz voltage-controlled oscillator in 90 nm CMOS with high-quality thin-film post-processed inductor. CICC Dimitri Linten, Xiao Sun, Geert Carchon, Wutthinan Jeamsaksiri, Abdelkarim Mercha, Javier Ramos, Snezana Jenei, Lars Aspemyr, Andries J. Scholten, Piet Wambacq, Stefaan Decoutere, Stéphane Donnay, Walter De Raedt
2004	—	`conf`	A 5 GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS. ESSCIRC Dimitri Linten, Steven Thijs, Mahadeva Iyer Natarajan, Piet Wambacq, Wutthinan Jeamsaksiri, Javier Ramos, Abdelkarim Mercha, Snezana Jenei, Stéphane Donnay, Stefaan Decoutere
2004	A	`conf`	Digital Ground Bounce Reduction by Phase Modulation of the Clock. DATE Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2004	J	`jnl`	Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. IEEE J. Solid State Circuits Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Lakshmanan Balasubramanian, Kris Tiri, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man
2004	A*	`conf`	High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. DAC Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2004	—	`conf`	Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs]. CICC Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2004	—	`conf`	Performance degradation of an LC-tank VCO by impact of digital switching noise. ESSCIRC Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay
2003	—	`conf`	A linear high voltage charge pump for MEMs applications in 0.18μm CMOS technology. ESSCIRC Manuel Innocent, Piet Wambacq, Stéphane Donnay, Willy Sansen, Hugo De Man
2003	J	`jnl`	An analytic Volterra-series-based model for a MEMS variable capacitor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Manuel Innocent, Piet Wambacq, Stéphane Donnay, Harrie A. C. Tilmans, Willy M. C. Sansen, Hugo De Man
2003	A	`conf`	Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits. DATE Petr Dobrovolný, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay
2003	J	`jnl`	Analysis and compact behavioral modeling of nonlinear distortion in analog communication circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Petr Dobrovolný, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay
2003	A	`conf`	Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver. DATE Wolfgang Eberle, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2003	—	`conf`	Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. ESSCIRC Mustafa Badaroglu, Lakshmanan Balasubramanian, Kris Tiri, Vincent Gravot, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
2002	A	`conf`	Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach . DATE Michaël Goffioul, Piet Wambacq, Gerd Vandersteen, Stéphane Donnay
2002	A*	`conf`	Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. DAC Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen
2002	A	`conf`	High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions. DATE Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Frans Verbeyst
2001	J	`jnl`	A Mixed-Signal Design Roadmap. IEEE Des. Test Comput. Ralf Brederlow, Werner Weber, Joseph Sauerer, Stéphane Donnay, Piet Wambacq, Maarten Vertregt
2001	A	`conf`	CAD for RF circuits. DATE Piet Wambacq, Gerd Vandersteen, Joel R. Phillips, Jaijeet S. Roychowdhury, Wolfgang Eberle, Baolin Yang, David E. Long, Alper Demir
2001	A	`conf`	Efficient bit-error-rate estimation of multicarrier transceivers. DATE Gerd Vandersteen, Piet Wambacq, Yves Rolain, Johan Schoukens, Stéphane Donnay, Marc Engels, Ivo Bolsens
2000	A*	`conf`	A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers. DAC Gerd Vandersteen, Piet Wambacq, Yves Rolain, Petr Dobrovolný, Stéphane Donnay, Marc Engels, Ivo Bolsens
2000	J	`jnl`	Analysis and experimental verification of digital substrate noise generation for epi-type substrates. IEEE J. Solid State Circuits Marc van Heijningen, John Compiet, Piet Wambacq, Stéphane Donnay, Marc Engels, Ivo Bolsens
2000	J	`jnl`	Chip-package codesign of a low-power 5-GHz RF front end. Proc. IEEE Stéphane Donnay, Philip Pieters, Kristof Vaesen, Wim Diels, Piet Wambacq, Walter De Raedt, Eric Beyne, Marc Engels, Ivo Bolsens
2000	A	`conf`	Compact Modeling of Nonlinear Distortion in Analog Communication Circuits. DATE Piet Wambacq, Petr Dobrovolný, Stéphane Donnay, Marc Engels, Ivo Bolsens
1999	A	`conf`	A Single-Package Solution for Wireless Transceivers. DATE Piet Wambacq, Stéphane Donnay, Hocine Ziad, Marc Engels, Hugo De Man, Ivo Bolsens
1999	—	`conf`	High-level simulation and power modelling of mixed-signal front-ends for digital telecommunications. ICECS Piet Wambacq, Gerd Vandersteen, Stéphane Donnay, Marc Engels, Ivo Bolsens, Erik Lauwers, Piet Vanassche, Georges G. E. Gielen
1995	J	`jnl`	Efficient symbolic computation of approximated small-signal characteristics of analog integrated circuits. IEEE J. Solid State Circuits Piet Wambacq, Francisco V. Fernández, Georges G. E. Gielen, Willy Sansen, Ángel Rodríguez-Vázquez
1995	C	`conf`	Use of Symbolic Analysis in Analog Circuit Synthesis. ISCAS Georges G. E. Gielen, Geert Debyser, Piet Wambacq, Koen Swings, Willy M. C. Sansen
1994	C	`conf`	Symbolic Analysis of Large Analog Integrated Circuits by Approximation During Expression Generation. ISCAS Francisco V. Fernández, Piet Wambacq, Georges G. E. Gielen, Ángel Rodríguez-Vázquez, Willy M. C. Sansen
1994	J	`jnl`	Symbolic analysis methods and applications for analog circuits: a tutorial overview. Proc. IEEE Georges G. E. Gielen, Piet Wambacq, Willy M. C. Sansen
1991	—	`conf`	Interactive symbolic distortion analysis of analogue integrated circuits. EURO-DAC Piet Wambacq, Georges G. E. Gielen, Willy Sansen
1989	J	`jnl`	On the relationship between the CMRR or PSRR and the second harmonic distortion of differential input amplifiers. IEEE J. Solid State Circuits Frank Op't Eynde, Piet Wambacq, Willy Sansen