Pierre G. Paulin

76 papers A* 10A 10C 9Misc 3Journal 21Unranked 20
YearRankTypeTitle / Venue / Authors
2014 — conf
Fast and accurate implementation of Canny edge detector on embedded many-core platform.
NEWCAS
Taieb Lamine Ben Cheikh, Gabriela Nicolescu, Jelena Trajkovic, Youcef Bouchebaba, Pierre G. Paulin
2013 — conf
A dynamic stream link for efficient data flow control in NoC based heterogeneous MPSoC.
ASP-DAC
Claude Helmstetter, Sylvain Basset, Romain Lemaire, Fabien Clermidy, Pascal Vivet, Michel Langevin, Chuck Pilkington, Pierre G. Paulin, Didier Fuin
2013 Misc conf
A novel compilation approach for image processing graphs on a many-core platform with explicitly managed memory.
CASES
Thierry Lepley, Pierre G. Paulin, Eric Flamand
2013 — conf
Mapping data-intensive applications to an explicitly managed memory architecture: Challenges and solutions.
ESTIMedia
Pierre G. Paulin
2013 J jnl
Parallel programming patterns for multi-processor SoC: Application to video processing.
ACM Trans. Embed. Comput. Syst.
Pierre G. Paulin, Ali Erdem Özcan, Vincent Gagné, Bruno Lavigueur, Olivier Benny
2013 J jnl
Reduction methods for adapting optical network on chip topologies to 3D architectures.
Microprocess. Microsystems
Sébastien Le Beux, Ian O'Connor, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin
2012 J jnl
Integrating Memory Optimization with Mapping Algorithms for Multi-Processors System-on-Chip.
ACM Trans. Embed. Comput. Syst.
Bruno Girodias, Luiza Gheorghe Iugan, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Michel Langevin, Pierre G. Paulin
2012 J jnl
MpAssign: a framework for solving the many-core platform mapping problem.
Softw. Pract. Exp.
Youcef Bouchebaba, Ali Erdem Özcan, Pierre G. Paulin, Gabriela Nicolescu
2012 — conf
On the Verification of a WiMax Design Using Symbolic Simulation.
SCSS
Salim Ismail Al-Akhras, Sofiène Tahar, Gabriela Nicolescu, Michel Langevin, Pierre G. Paulin
2011 A conf
Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology.
DATE
Sébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin
2011 A* conf
Programming challenges & solutions for multi-processor SoCs: an industrial perspective.
DAC
Pierre G. Paulin
2010 C conf
A system-level exploration flow for optica network on chip (ONoC) in 3D MPSoC.
ISCAS
Sébastien Le Beux, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin
2010 J jnl
Combining mapping and partitioning exploration for NoC-based embedded systems.
J. Syst. Archit.
Sébastien Le Beux, Guy Bois, Gabriela Nicolescu, Youcef Bouchebaba, Michel Langevin, Pierre G. Paulin
2010 C conf
Combining memory optimization with mapping of multimedia applications for multi-processors system-on-chip.
International Symposium on Rapid System Prototyping
Bruno Girodias, Luiza Gheorghe, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Michel Langevin, Pierre G. Paulin
2010 C conf
MpAssign: A framework for solving the many-core platform mapping problem.
International Symposium on Rapid System Prototyping
Youcef Bouchebaba, Pierre G. Paulin, Ali Erdem Özcan, Bruno Lavigueur, Michel Langevin, Olivier Benny, Gabriela Nicolescu
2010 J jnl
Multi-Optical Network-on-Chip for Large Scale MPSoC.
IEEE Embed. Syst. Lett.
Sébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin
2009 J jnl
Multiprocessor, Multithreading and Memory Optimization for On-Chip Multimedia Applications.
J. Signal Process. Syst.
Bruno Girodias, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Pierre G. Paulin, Bruno Lavigueur
2009 — conf
Optimizing Configuration and Application Mapping for MPSoC Architectures.
AHS
Sébastien Le Beux, Gabriela Nicolescu, Guy Bois, Youcef Bouchebaba, Michel Langevin, Pierre G. Paulin
2008 A* conf
Multicore design is the challenge! what is the solution?
DAC
Eshel Haritan, Toshihiro Hattori, Hiroyuki Yagi, Pierre G. Paulin, Wayne H. Wolf, Achim Nohl, Drew Wingard, Mike Muller
2008 Misc conf
Reliable performance analysis of a multicore multithreaded system-on-chip.
CODES+ISSS
Simon Schliecker, Mircea Negrean, Gabriela Nicolescu, Pierre G. Paulin, Rolf Ernst
2007 A conf
A future of customizable processors: are we there yet?
DATE
Laura Pozzi, Pierre G. Paulin
2007 — conf
An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept.
ICECS
Karim Hadjiat, Francis St-Pierre, Guy Bois, Yvon Savaria, Michel Langevin, Pierre G. Paulin
2007 C conf
MPSoC memory optimization for digital camera applications.
DSD
Youcef Bouchebaba, Bruno Lavigueur, Bruno Girodias, Gabriela Nicolescu, Pierre G. Paulin
2007 J jnl
MPSoC memory optimization using program transformation.
ACM Trans. Design Autom. Electr. Syst.
Youcef Bouchebaba, Bruno Girodias, Gabriela Nicolescu, El Mostapha Aboulhamid, Bruno Lavigueur, Pierre G. Paulin
2007 J jnl
Roundtable: Design and CAD Challenges for Leading-Edge Multimedia Designs.
IEEE Des. Test Comput.
Andrew B. Kahng, Ira Chayut, John M. Cohn, Toshihiro Hattori, Jeong-Taek Kong, Pierre G. Paulin, Rich Tobias
2007 J jnl
Roundtable: Envisioning the Future for Multiprocessor SoC.
IEEE Des. Test Comput.
Ahmed Amine Jerraya, Olivier Franza, Markus Levy, Masao Nakaya, Pierre G. Paulin, Ulrich Ramacher, Deepu Talla, Wayne H. Wolf
2007 — conf
Two-level tiling for MPSoC architecture.
ASAP
Youcef Bouchebaba, Essaid Bensoudane, Bruno Lavigueur, Pierre G. Paulin, Gabriela Nicolescu
2006 C conf
An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures.
VLSI-SoC
Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Pierre G. Paulin, Essaid Bensoudane
2006 C conf
Application-Level Memory Optimization for MPSoC.
IEEE International Workshop on Rapid System Prototyping
Bruno Girodias, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Pierre G. Paulin, Bruno Lavigueur
2006 A conf
Distributed object models for multi-processor SoC's, with application to low-power multimedia wireless systems.
DATE
Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Olivier Benny, Damien Lyonnard, Bruno Lavigueur, David Lo
2006 J jnl
Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia.
IEEE Trans. Very Large Scale Integr. Syst.
Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Damien Lyonnard, Olivier Benny, Bruno Lavigueur, David Lo, Giovanni Beltrame, Vincent Gagné, Gabriela Nicolescu
2005 — ch.
A Multiprocessor SoC Platform and Tools for Communications Applications.
Embedded Systems Handbook
Essaid Bensoudane, Gabriela Nicolescu, Pierre G. Paulin, Michel Langevin, Chuck Pilkington, Damien Lyonnard
2004 A conf
Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding.
DATE
Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane, Michel Langevin, Damien Lyonnard
2004 C conf
Automatic Mapping of Parallel Applications onto Multi-Processor Platforms: A Multimedia Application.
DSD
Pierre G. Paulin
2004 A conf
DATE Panel: Chips of the Future: Soft, Crunchy or Hard?
DATE
Pierre G. Paulin
2004 — conf
Designing High Quality, Scaleable SoC??s with Heterogeneous Components.
ISQED
Pierre G. Paulin
2004 Misc conf
Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management.
CODES+ISSS
Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Gabriela Nicolescu
2004 A* conf
System level design: six success stories in search of an industry.
DAC
Francine Bacchini, Pierre G. Paulin, Reinaldo A. Bergamaschi, Raj Pawate, Arie Bernstein, Ramesh Chandra, Mohamed Ben-Romdhane
2003 A conf
Network Processing Challenges and an Experimental NPU Platform.
DATE
Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane
2003 A* conf
System-on-chip beyond the nanometer wall.
DAC
Philippe Magarshack, Pierre G. Paulin
2002 J jnl
FlexWare: A Retargetable Embedded-Software Development Environment.
IEEE Des. Test Comput.
Pierre G. Paulin, Miguel Santana
2002 J jnl
StepNP: A System-Level Exploration Platform for Network Processors.
IEEE Des. Test Comput.
Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane
2002 A conf
Who Owns the Platform?
DATE
Vassilios Gerousis, Oz Levia, Pierre G. Paulin, Mark Pinto, Chris Rowen, Gabriele Saucier
2001 — conf
Embedded systems technologies for application-specific architecture platforms.
ISSS
Pierre G. Paulin
2001 A conf
Network processors: a perspective on market requirements, processor architectures and embedded S/W tools.
DATE
Pierre G. Paulin, Faraydon Karim, Paul Bromley
2001 — conf
Programming models for network processors (Panel).
ISSS
Ahmed Amine Jerraya, Pierre G. Paulin, Richard Norman, Feliks J. Welfeld
2000 A conf
The Future of Flexible HW Platform Architectures Panel Discussion.
DATE
Rolf Ernst, Grant Martin, Oz Levia, Pierre G. Paulin, Stamatis Vassiliadis, Kees A. Vissers
2000 — conf
Towards Application-Specific Architecture Platforms: Embedded Systems Design Automation Technologies.
EUROMICRO
Pierre G. Paulin
1998 J jnl
Automatic VHDL-C Interface Generation for Distributed Cosimulation: Application to Large Design Examples.
Des. Autom. Embed. Syst.
Carlos A. Valderrama, François Naçabal, Pierre G. Paulin, Ahmed Amine Jerraya
1997 A* conf
Am Embedded System Case Study: The Firm Ware Development Environment for a Multimedia Audio Processor.
DAC
Clifford Liem, Marco Cornero, Miguel Santana, Pierre G. Paulin, Ahmed Amine Jerraya, Jean-Marc Gentit, Jean Lopez, Xavier Figari, Laurent Bergher
1997 J jnl
Compilation Methods for the Address Calculation Units of Embedded Processor Systems.
Des. Autom. Embed. Syst.
Clifford Liem, Pierre G. Paulin, Ahmed Amine Jerraya
1997 J jnl
Embedded software in real-time signal processing systems: application and architecture trends.
Proc. IEEE
Pierre G. Paulin, Clifford Liem, Marco Cornero, François Naçabal, Gert Goossens
1997 J jnl
Embedded software in real-time signal processing systems: design technologies.
Proc. IEEE
Gert Goossens, Johan Van Praet, Dirk Lanneer, Werner Geurts, Augusli Kifli, Clifford Liem, Pierre G. Paulin
1997 — conf
ReCode: the design and re-design of the instruction codes for embedded instruction-set processors.
ED&TC
Clifford Liem, Pierre G. Paulin, Ahmed Amine Jerraya
1997 J jnl
System-on-a-Chip Cosimulation and Compilation.
IEEE Des. Test Comput.
Clifford Liem, François Naçabal, Carlos A. Valderrama, Pierre G. Paulin, Ahmed Amine Jerraya
1996 A* conf
Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures.
DAC
Clifford Liem, Pierre G. Paulin, Ahmed Amine Jerraya
1996 C conf
Automatic generation of interfaces for distributed C-VHDL cosimulation of embedded systems: an industrial experience.
RSP
Carlos A. Valderrama, François Naçabal, Pierre G. Paulin, Ahmed Amine Jerraya
1995 J jnl
DSP design tool requirements for embedded systems: A telecommunications industrial perspective.
J. VLSI Signal Process.
Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala
1995 — conf
High-level synthesis and codesign methods: an application to a videophone codec.
EURO-DAC
Pierre G. Paulin, Jean Fréhel, Michel Harrand, Elisabeth Berrebi, Clifford Liem, François Naçabal, Jean-Claude Herluison
1995 — conf
Industrial experience using rule-driven retargetable code generation for multimedia applications.
ISSS
Clifford Liem, Pierre G. Paulin, Marco Cornero, Ahmed Amine Jerraya
1995 — ed.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France
ISSS
Pierre G. Paulin, Farhad Mavaddat
1994 — conf
CodeSyn: a retargetable code synthesis system (abstract).
HLSS
Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala
1994 — conf
Flexible modeling environment for embedded systems design.
CODES
Shailesh Sutarwala, Pierre G. Paulin
1994 — conf
Flexware: A flexible firmware development environment for embedded systems.
Code Generation for Embedded Processors
Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala
1994 — conf
Instruction-Set Matching and Selection for DSP and ASIP Code Generation.
EDAC-ETC-EUROASIC
Clifford Liem, Trevor C. May, Pierre G. Paulin
1994 — ed.
Proceedings of the 7th International Symposium on High Level Synthesis, HLSS'94, Niagra-on-the-Lake, ON, Canada, May 18-20, 1994
HLSS
Pierre G. Paulin
1994 A conf
Register assignment through resource classification for ASIP microcode generation.
ICCAD
Clifford Liem, Trevor C. May, Pierre G. Paulin
1993 — conf
Insulin: An Instruction Set Simulation Environment.
CHDL
Shailesh Sutarwala, Pierre G. Paulin, Yatish Kumar
1991 — conf
Meta VHDL for Higher Level Controller Modeling and Synthesis.
VLSI
Ahmed Amine Jerraya, Pierre G. Paulin, Simon Curry
1989 J jnl
Algorithms for high-level synthesis.
IEEE Des. Test
Pierre G. Paulin, John P. Knight
1989 J jnl
Force-directed scheduling for the behavioral synthesis of ASICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pierre G. Paulin, John P. Knight
1989 A* conf
Horizontal Partitioning of PLA-based Finite State Machines.
DAC
Pierre G. Paulin
1989 C conf
Logic decomposition algorithms for the timing optimization of multi-level logic.
ICCD
Pierre G. Paulin, Franck J. Poirot
1989 A* conf
Scheduling and Binding Algorithms for High-Level Synthesis.
DAC
Pierre G. Paulin, John P. Knight
1987 A* conf
Force-Directed Scheduling in Automatic Data Path Synthesis.
DAC
Pierre G. Paulin, John P. Knight
1986 A* conf
HAL: a multi-paradigm approach to automatic data path synthesis.
DAC
Pierre G. Paulin, John P. Knight, Emil F. Girczyc