Pierre-Emmanuel Gaillardon

199 papers A* 12A 31B 4C 29Journal 59Unranked 60

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Automated Generation of Microfluidic Netlists using Large Language Models. CoRR Jasper Davidson, Skylar Stockham, Allen Boston, Ashton Snelgrove, Valerio Tenace, Pierre-Emmanuel Gaillardon
2026	J	`jnl`	OpenFPGA-NoC: Automated Fabric and Bitstream Generation for NoC-based FPGAs. ACM Trans. Reconfigurable Technol. Syst. Ruthwik Reddy Sunketa, Muhammad Ali Farooq, Ganesh Gore, Allen Boston, Pierre-Emmanuel Gaillardon, Aman Arora
2025	J	`jnl`	ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction. CoRR Luca Collini, Jitendra Bhandari, Chiara Muscari Tomajoli, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Xifan Tang, Pierre-Emmanuel Gaillardon, Ramesh Karri, Christian Pilato
2025	J	`jnl`	ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction. ACM Trans. Design Autom. Electr. Syst. Luca Collini, Jitendra Bhandari, Chiara Muscari Tomajoli, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Xifan Tang, Pierre-Emmanuel Gaillardon, Ramesh Karri, Christian Pilato
2025	J	`jnl`	Adaptive Multi-Agent Reasoning via Automated Workflow Generation. CoRR Humza Sami, Mubashir ul Islam, Pierre-Emmanuel Gaillardon, Valerio Tenace
2025	C	`conf`	Automated Generation of Microfluidic Netlists using Large Language Models. VLSI-SoC Jasper Davidson, Skylar Stockham, Allen Boston, Ashton Snelgrove, Valerio Tenace, Pierre-Emmanuel Gaillardon
2025	J	`jnl`	Changing Idling Behavior Through Dynamic Idle Detection and Air Quality Messaging. IEEE Internet Things J. Tristalee Mangin, Xiwen Li, Saba Mahmoudi, Rehman Mohammed, Nathan Page, Sara Peck, Ashton Snelgrove, Evan Blanchard, Dillon Tang, Lizzie Pinegar, Owen Leishman, J. Nicholas Rice, Gregory Madden, Pierre-Emmanuel Gaillardon, Ross T. Whitaker, Kerry E. Kelly
2025	A	`conf`	EDA-Aware RTL Generation with Large Language Models. DATE Mubashir ul Islam, Humza Sami, Pierre-Emmanuel Gaillardon, Valerio Tenace
2025	C	`conf`	Lightweight Congruence Profiling for Early Design Exploration of Heterogeneous FPGAs. VLSI-SoC Allen Boston, Biruk B. Seyoum, Luca P. Carloni, Pierre-Emmanuel Gaillardon
2025	J	`jnl`	Lightweight Congruence Profiling for Early Design Exploration of Heterogeneous FPGAs. CoRR Allen Boston, Biruk B. Seyoum, Luca P. Carloni, Pierre-Emmanuel Gaillardon
2025	J	`jnl`	Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation. CoRR Humza Sami, Mubashir ul Islam, Samy Charas, Asav Gandhi, Pierre-Emmanuel Gaillardon, Valerio Tenace
2025	A	`conf`	OpenMFDA: Microfluidic Design Automation in Three Dimensions. DATE Ashton Snelgrove, Daniel Wakeham, Skylar Stockham, Scott Temple, Pierre-Emmanuel Gaillardon
2024	J	`jnl`	AIvril: AI-Driven RTL Generation With Verification In-The-Loop. CoRR Mubashir ul Islam, Humza Sami, Pierre-Emmanuel Gaillardon, Valerio Tenace
2024	C	`conf`	Benchmarking Microfluidic Design Automation Flows. VLSI-SoC Ashton Snelgrove, Skylar Stockham, Pierre-Emmanuel Gaillardon
2024	J	`jnl`	EDA-Aware RTL Generation with Large Language Models. CoRR Mubashir ul Islam, Humza Sami, Pierre-Emmanuel Gaillardon, Valerio Tenace
2024	—	`conf`	Secure eFPGA Configuration: A System-Level Approach. ARC Allen Boston, Roman Gauchi, Pierre-Emmanuel Gaillardon
2024	—	`conf`	Selecting IRN for AFE to Achieve Power-Area-Noise Efficiency in Next-Generation Neural Implants. MWSCAS Seyed Mohammad Ali Zeinolabedin, Matthieu Couriol, Pierre-Emmanuel Gaillardon
2023	J	`jnl`	A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA Design. IEEE Trans. Very Large Scale Integr. Syst. Ganesh Gore, Xifan Tang, Pierre-Emmanuel Gaillardon
2023	J	`jnl`	CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration. ACM Trans. Reconfigurable Technol. Syst. Aman Arora, Atharva Bhamburkar, Aatman Borda, Tanmay Anand, Rishabh Sehgal, Bagus Hanindhito, Pierre-Emmanuel Gaillardon, Jaydeep P. Kulkarni, Lizy K. John
2023	J	`jnl`	FlowTune: End-to-End Automatic Logic Optimization Exploration via Domain-Specific Multiarmed Bandit. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Walter Lau Neto, Yingjie Li, Pierre-Emmanuel Gaillardon, Cunxi Yu
2023	J	`jnl`	Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking. IEEE Trans. Circuits Syst. I Regul. Pap. Aurélien Alacchi, Edouard Giacomin, Scott Temple, Roman Gauchi, Michael J. Wirthlin, Pierre-Emmanuel Gaillardon
2023	J	`jnl`	NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report. CoRR Matthew Guthaus, Christopher Batten, Erik Brunvand, Pierre-Emmanuel Gaillardon, David M. Harris, Rajit Manohar, Pinaki Mazumder, Larry T. Pileggi, James E. Stine
2023	J	`jnl`	Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction. IEEE Trans. Very Large Scale Integr. Syst. Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri
2023	A	`conf`	Open-source and FPGAs: Hardware, Software, Both or None? FPGA Dana How, Tim Ansell, Vaughn Betz, Chris Lavin, Ted Speers, Pierre-Emmanuel Gaillardon
2023	—	`conf`	Performance Optimized Clock Tree Embedding for Auto-Generated FPGAs. ISVLSI Grant Brown, Ganesh Gore, Pierre-Emmanuel Gaillardon
2023	J	`jnl`	Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures. IEEE Trans. Very Large Scale Integr. Syst. Aurélien Alacchi, Edouard Giacomin, Roman Gauchi, Szymon Kulis, Pierre-Emmanuel Gaillardon
2022	J	`jnl`	A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gabriel Ammes, Walter Lau Neto, Paulo F. Butzen, Pierre-Emmanuel Gaillardon, Renato P. Ribas
2022	J	`jnl`	ALICE: An Automatic Design Flow for eFPGA Redaction. CoRR Chiara Muscari Tomajoli, Luca Collini, Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Xifan Tang, Pierre-Emmanuel Gaillardon, Ramesh Karri, Christian Pilato
2022	A*	`conf`	ALICE: an automatic design flow for eFPGA redaction. DAC Chiara Muscari Tomajoli, Luca Collini, Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Xifan Tang, Pierre-Emmanuel Gaillardon, Ramesh Karri, Christian Pilato
2022	C	`conf`	An Energy-Efficient Three-Independent-Gate FET Cell Library for Low-Power Edge Computing. VLSI-SoC Michael Keyser, Roman Gauchi, Pierre-Emmanuel Gaillardon
2022	C	`conf`	An Open-source Three-Independent-Gate FET Standard Cell Library for Mixed Logic Synthesis. ISCAS Roman Gauchi, Ashton Snelgrove, Pierre-Emmanuel Gaillardon
2022	J	`jnl`	End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Bandit. CoRR Walter Lau Neto, Yingjie Li, Pierre-Emmanuel Gaillardon, Cunxi Yu
2022	A*	`conf`	Improving LUT-based optimization for ASICs. DAC Walter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon
2022	J	`jnl`	Programmable Local Clock SET Filtering for SEE-Resistant FPGA. IEEE Trans. Circuits Syst. II Express Briefs Aurélien Alacchi, Pierre-Emmanuel Gaillardon
2022	C	`conf`	Programmable logic elements using multigate ambipolar transistors. DDECS Ashton Snelgrove, Pierre-Emmanuel Gaillardon
2022	—	`conf`	Tiny Time-Series Transformers: Realtime Multi-Target Sensor Inference At The Edge. COINS Thomas Becnel, Kerry E. Kelly, Pierre-Emmanuel Gaillardon
2021	C	`conf`	A 12-pA Resolution Sigma Delta ADC Topology for Chemiresistive Sensor-Based Applications. VLSI-SoC Matthieu Couriol, Edouard Giacomin, Pierre-Emmanuel Gaillardon
2021	A	`conf`	A Deep Learning Approach to Sensor Fusion Inference at the Edge. DATE Thomas Becnel, Pierre-Emmanuel Gaillardon
2021	—	`conf`	A First Approach in Using Super-Steep-Subthreshold-Slope Field-Effect Transistors in Ultra-Low Power Analog Design. VLSI-SoC (Selected Papers) Matthieu Couriol, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon
2021	C	`conf`	A Novel High-Gain Amplifier Circuit Using Super-Steep-Subthreshold-Slope Field-Effect Transistors. VLSI-SoC Matthieu Couriol, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon
2021	—	`conf`	A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs. ISPD Ganesh Gore, Xifan Tang, Pierre-Emmanuel Gaillardon
2021	J	`jnl`	A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. CoRR Gabriel Ammes, Walter Lau Neto, Paulo F. Butzen, Pierre-Emmanuel Gaillardon, Renato P. Ribas
2021	C	`conf`	Area-Efficient Multiplier Designs Using a 3D Nanofabric Process Flow. ISCAS Edouard Giacomin, Francky Catthoor, Pierre-Emmanuel Gaillardon
2021	A	`conf`	Exploring eFPGA-based Redaction for IP Protection. ICCAD Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri
2021	J	`jnl`	Exploring eFPGA-based Redaction for IP Protection. CoRR Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri
2021	J	`jnl`	Guest Editors' Introduction: The Resurgence of Open- Source EDA Technology. IEEE Des. Test Sherief Reda, Leon Stok, Pierre-Emmanuel Gaillardon
2021	A*	`conf`	Invited: Getting the Most out of your Circuits with Heterogeneous Logic Synthesis. DAC Scott Temple, Walter Lau Neto, Ashton Snelgrove, Xifan Tang, Pierre-Emmanuel Gaillardon
2021	A	`conf`	Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
2021	—	`conf`	NEMO-CNN: An Efficient Near-Memory Accelerator for Convolutional Neural Networks. ASAP Grant Brown, Valerio Tenace, Pierre-Emmanuel Gaillardon
2021	J	`jnl`	Not All Fabrics Are Created Equal: Exploring eFPGA Parameters For IP Redaction. CoRR Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri
2021	—	`conf`	Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization. ASP-DAC Walter Lau Neto, Matheus Trevisan Moreira, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon
2021	A*	`conf`	SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping. DAC Walter Lau Neto, Matheus T. Moreira, Yingjie Li, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon
2021	C	`conf`	Smart-Redundancy: An Alternative SEU/SET Mitigation Method for FPGAs. ISCAS Aurélien Alacchi, Edouard Giacomin, Xifan Tang, Pierre-Emmanuel Gaillardon
2021	B	`conf`	Taping out an FPGA in 24 hours with OpenFPGA: The SOFA Project. FPL Xifan Tang, Ganesh Gore, Grant Brown, Pierre-Emmanuel Gaillardon
2021	—	`ed.`	VLSI-SoC: Design Trends - 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers VLSI-SoC (Selected Papers) Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis
2021	J	`jnl`	multiPULPly: A Multiplication Engine for Accelerating Neural Networks on Ultra-low-power Architectures. ACM J. Emerg. Technol. Comput. Syst. Adi Eliahu, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky
2020	—	`conf`	3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs. VLSI-SoC (Selected Papers) Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon
2020	A	`conf`	A Novel TIGFET-based DFF Design for Improved Resilience to Power Side-Channel Attacks. DATE Mohammad Mehdi Sharifi, Ramin Rajaei, Patsy Cadareanu, Pierre-Emmanuel Gaillardon, Yier Jin, Michael T. Niemier, Xiaobo Sharon Hu
2020	A	`conf`	A RRAM-based FPGA for Energy-efficient Edge Computing. DATE Xifan Tang, Edouard Giacomin, Patsy Cadareanu, Ganesh Gore, Pierre-Emmanuel Gaillardon
2020	A	`conf`	A Scalable Mixed Synthesis Framework for Heterogeneous Networks. DATE Max Austin, Scott Temple, Walter Lau Neto, Luca G. Amarù, Xifan Tang, Pierre-Emmanuel Gaillardon
2020	J	`jnl`	Exact Benchmark Circuits for Logic Synthesis. IEEE Des. Test Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, Pierre-Emmanuel Gaillardon, André Inácio Reis, Renato Perez Ribas
2020	J	`jnl`	Extending Boolean Methods for Scalable Logic Synthesis. IEEE Access Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2020	C	`conf`	Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow. VLSI-SOC Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon
2020	J	`jnl`	Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
2020	J	`jnl`	OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs. IEEE Micro Xifan Tang, Edouard Giacomin, Baudouin Chauviere, Aurélien Alacchi, Pierre-Emmanuel Gaillardon
2020	A*	`conf`	SpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks. ISCA Surya Narayanan, Karl Taht, Rajeev Balasubramonian, Edouard Giacomin, Pierre-Emmanuel Gaillardon
2020	—	`ed.`	VLSI-SoC: New Technology Enabler - 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6-9, 2019, Revised and Extended Selected Papers VLSI-SoC (Selected Papers) Carolina Metzler, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Carlos Silva Cárdenas, Ricardo Reis
2019	J	`jnl`	A Distributed Low-Cost Pollution Monitoring Platform. IEEE Internet Things J. Thomas Becnel, Kyle Tingey, Jonathan Whitaker, Tofigh Sayahi, Katrina Lê, Pascal Goffin, Anthony Butterfield, Kerry E. Kelly, Pierre-Emmanuel Gaillardon
2019	—	`conf`	A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors. VLSI-SoC (Selected Papers) Patsy Cadareanu, Ganesh Gore, Edouard Giacomin, Pierre-Emmanuel Gaillardon
2019	C	`conf`	A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors. VLSI-SoC Ganesh Gore, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon
2019	C	`conf`	A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories. VLSI-SoC João Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon
2019	—	`conf`	A Recursive Approach to Partially Blind Calibration of a Pollution Sensor Network. ICESS Thomas Becnel, Tofigh Sayahi, Kerry E. Kelly, Pierre-Emmanuel Gaillardon
2019	J	`jnl`	A Robust Digital RRAM-Based Convolutional Block for Low-Power Image Processing and Learning Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Edouard Giacomin, Tzofnat Greenberg-Toledo, Shahar Kvatinsky, Pierre-Emmanuel Gaillardon
2019	—	`conf`	A Study on Switch Block Patterns for Tileable FPGA Routing Architectures. FPT Xifan Tang, Edouard Giacomin, Aurélien Alacchi, Pierre-Emmanuel Gaillardon
2019	—	`ch.`	A Taxonomy and Evaluation Framework for Memristive Logic. Handbook of Memristor Networks John Reuben, Nishil Talati, Nimrod Wald, Rotem Ben Hur, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky
2019	—	`conf`	Accelerating Inference on Binary Neural Networks with Digital RRAM Processing. VLSI-SoC (Selected Papers) João Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon
2019	J	`jnl`	Devices and Circuits Using Novel 2-D Materials: A Perspective for Future VLSI Systems. IEEE Trans. Very Large Scale Integr. Syst. Giovanni V. Resta, Alessandra Leonhardt, Yashwanth Balaji, Stefan De Gendt, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2019	J	`jnl`	FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
2019	—	`conf`	Functionality Enhanced Memories for Edge-AI Embedded Systems. NVMTS Alexandre Levisse, Marco Rios, William Andrew Simon, Pierre-Emmanuel Gaillardon, David Atienza
2019	A*	`conf`	GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment. MICRO Anirban Nag, C. N. Ramachandra, Rajeev Balasubramonian, Ryan Stutsman, Edouard Giacomin, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon
2019	—	`conf`	Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs. ISVLSI Walter Lau Neto, Xifan Tang, Max Austin, Luca G. Amarù, Pierre-Emmanuel Gaillardon
2019	A	`conf`	LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper. ICCAD Walter Lau Neto, Max Austin, Scott Temple, Luca G. Amarù, Xifan Tang, Pierre-Emmanuel Gaillardon
2019	—	`ch.`	Memory Effects in Multi-terminal Solid State Devices and Their Applications. Handbook of Memristor Networks Davide Sacchetto, Pierre-Emmanuel Gaillardon, Yusuf Leblebici, Giovanni De Micheli
2019	B	`conf`	OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs. FPL Xifan Tang, Edouard Giacomin, Aurélien Alacchi, Baudouin Chauviere, Pierre-Emmanuel Gaillardon
2019	A	`conf`	Rebooting Our Computing Models. DATE Patsy Cadareanu, N. Reddy C, Carmen G. Almudéver, A. Khanna, Arijit Raychowdhury, Suman Datta, Koen Bertels, Vijayakrishan Narayanan, Massimiliano Di Ventra, Pierre-Emmanuel Gaillardon
2019	A	`conf`	Scalable Boolean Methods in a Modern Synthesis Flow. DATE Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2019	A*	`conf`	Wire-Aware Architecture and Dataflow for CNN Accelerators. MICRO Sumanth Gudaparthi, Surya Narayanan, Rajeev Balasubramonian, Edouard Giacomin, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon
2018	—	`conf`	An Efficient Adder Architecture with Three- Independent-Gate Field-Effect Transistors. ICRC Jorge Romero Gonzalez, Pierre-Emmanuel Gaillardon
2018	C	`conf`	Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors. VLSI-SoC Edouard Giacomin, Pierre-Emmanuel Gaillardon
2018	—	`conf`	Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors. DRC Giovanni V. Resta, Yashwanth Balaji, Dennis Lin, Iuliana P. Radu, Francky Catthoor, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2018	A	`conf`	Emerging reconfigurable nanotechnologies: can they support future electronics? ICCAD Shubham Rai, Srivatsa Rangachar Srinivasa, Patsy Cadareanu, Xunzhao Yin, Xiaobo Sharon Hu, Pierre-Emmanuel Gaillardon, Vijaykrishnan Narayanan, Akash Kumar
2018	J	`jnl`	Guest Editorial Memristive-Device-Based Computing. IEEE Trans. Very Large Scale Integr. Syst. Said Hamdioui, Pierre-Emmanuel Gaillardon, Dietmar Fey, Tajana Simunic Rosing
2018	J	`jnl`	Logic Synthesis for RRAM-Based In-Memory Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
2018	J	`jnl`	Post-P&R Performance and Power Analysis for RRAM-Based FPGAs. IEEE J. Emerg. Sel. Topics Circuits Syst. Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
2018	A	`conf`	Practical challenges in delivering the promises of real processing-in-memory machines. DATE Nishil Talati, Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky
2018	A	`conf`	Towards high-performance polarity-controllable FETs with 2D materials. DATE Giovanni V. Resta, Jorge Romero Gonzalez, Yashwanth Balaji, Tarun Agarwal, Dennis Lin, Francky Catthoor, Iuliana P. Radu, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
2017	J	`jnl`	A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers. IEEE Trans. Emerg. Top. Comput. Xifan Tang, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
2017	J	`jnl`	A PLiM Computer for the Internet of Things. Computer Mathias Soeken, Pierre-Emmanuel Gaillardon, Saeideh Shirinzadeh, Rolf Drechsler, Giovanni De Micheli
2017	—	`conf`	A novel basis for logic rewriting. ASP-DAC Winston Haaswijk, Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2017	C	`conf`	An efficient electronic measurement interface for memristive biosensors. ISCAS Sebastien Naus, Ioulia Tzouvadaki, Pierre-Emmanuel Gaillardon, Armando Biscontini, Giovanni De Micheli, Sandro Carrara
2017	J	`jnl`	Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure. IEEE Trans. Circuits Syst. I Regul. Pap. Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
2017	C	`conf`	Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop. ISCAS Mahesh Nataraj, Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Pascal Andreas Meinerzhagen, Jean-Michel Portal, Pierre-Emmanuel Gaillardon
2017	A	`conf`	Enabling exact delay synthesis. ICCAD Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli
2017	A	`conf`	Endurance management for resistive Logic-In-Memory computing architectures. DATE Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler
2017	J	`jnl`	Exact Synthesis of Majority-Inverter Graphs and Its Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2017	—	`conf`	Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. ACM Great Lakes Symposium on VLSI Zhufei Chu, Xifan Tang, Mathias Soeken, Ana Petkovska, Grace Zgheib, Luca Gaetano Amarù, Yinshui Xia, Paolo Ienne, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
2017	—	`conf`	Low-power multiplexer designs using three-independent-gate field effect transistors. NANOARCH Edouard Giacomin, Jorge Romero Gonzalez, Pierre-Emmanuel Gaillardon
2017	—	`conf`	Memristive logic: A framework for evaluation and comparison. PATMOS John Reuben, Rotem Ben Hur, Nimrod Wald, Nishil Talati, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky
2017	—	`conf`	Multi-level logic benchmarks: An exactness study. ASP-DAC Luca Gaetano Amarù, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2017	—	`conf`	Optimization opportunities in RRAM-based FPGA architectures. LASCAS Xifan Tang, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
2017	—	`conf`	Physical Design Considerations of One-level RRAM-based Routing Multiplexers. ISPD Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
2017	C	`conf`	RM3 based logic synthesis (Special session paper). ISCAS Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2017	A	`conf`	Wave pipelining for majority-based beyond-CMOS technologies. DATE Odysseas Zografos, A. De Meester, Eleonora Testa, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Luca Gaetano Amarù, Praveen Raghavan, Francky Catthoor, Rudy Lauwereins
2016	J	`jnl`	A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors. ACM J. Emerg. Technol. Comput. Syst. Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Jian Zhang, Giovanni De Micheli, Ernesto Sánchez, Matteo Sonza Reorda
2016	A	`conf`	A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only). FPGA Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2016	J	`jnl`	A Sound and Complete Axiomatization of Majority-n Logic. IEEE Trans. Computers Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Anupam Chattopadhyay, Giovanni De Micheli
2016	J	`jnl`	A Study on the Programming Structures for RRAM-Based FPGA Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. Xifan Tang, Gain Kim, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2016	A*	`conf`	An MIG-based compiler for programmable logic-in-memory architectures. DAC Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli
2016	J	`jnl`	Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology. IEEE J. Emerg. Sel. Topics Circuits Syst. Jury Sandrini, Marios Barlas, Maxime Thammasack, Tugba Demirci, Michele De Marchi, Davide Sacchetto, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Yusuf Leblebici
2016	C	`conf`	Digital, analog and RF design opportunities of three-independent-gate transistors. ISCAS Pierre-Emmanuel Gaillardon, Mehdi Hasan, Anirban Saha, Luca Gaetano Amarù, Ross Walker, Berardi Sensale Rodriguez
2016	J	`jnl`	Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2016	J	`jnl`	Emerging Technology-Based Design of Primitives for Hardware Security. ACM J. Emerg. Technol. Comput. Syst. Yu Bi, Kaveh Shamsi, Jiann-Shiun Yuan, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Xunzhao Yin, Xiaobo Sharon Hu, Michael T. Niemier, Yier Jin
2016	A	`conf`	Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking. DATE Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Robert Wille, Giovanni De Micheli
2016	A	`conf`	Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs. DATE Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
2016	—	`conf`	Inversion optimization in Majority-Inverter Graphs. NANOARCH Eleonora Testa, Mathias Soeken, Odysseas Zografos, Luca Gaetano Amarù, Praveen Raghavan, Rudy Lauwereins, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2016	J	`jnl`	Majority-Inverter Graph: A New Paradigm for Logic Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2016	—	`conf`	Majority-based synthesis for nanotechnologies. ASP-DAC Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2016	—	`conf`	Notes on Majority Boolean Algebra. ISMVL Anupam Chattopadhyay, Luca Gaetano Amarù, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2016	A	`conf`	Optimizing Majority-Inverter Graphs with functional hashing. DATE Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2016	A	`conf`	The Programmable Logic-in-Memory (PLiM) computer. DATE Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Anne Siemon, Eike Linn, Rainer Waser, Anupam Chattopadhyay, Giovanni De Micheli
2016	—	`conf`	Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applications. LATS Pierre-Emmanuel Gaillardon, Romain Magni, Luca Gaetano Amarù, Mehdi Hasan, Ross Walker, Berardi Sensale Rodriguez, Jean-Frédéric Christmann, Edith Beigné
2015	J	`jnl`	A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells. IEEE Trans. Very Large Scale Integr. Syst. Pierre-Emmanuel Gaillardon, Xifan Tang, Gain Kim, Giovanni De Micheli
2015	J	`jnl`	A Sound and Complete Axiomatization of Majority-n Logic. CoRR Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Anupam Chattopadhyay, Giovanni De Micheli
2015	J	`jnl`	A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems. ACM J. Emerg. Technol. Comput. Syst. Pierre-Emmanuel Gaillardon, Edith Beigné, Suzanne Lesecq, Giovanni De Micheli
2015	—	`conf`	A fast pruning technique for low-power inexact Circuit design. LASCAS Johan Broc, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Jaume Joven Murillo, Krishna V. Palem, Giovanni De Micheli
2015	—	`conf`	A study on buffer distribution for RRAM-based FPGA routing structures. LASCAS Somayyeh Rahimian Omam, Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2015	—	`conf`	A surface potential and current model for polarity-controllable silicon nanowire FETs. ESSDERC Jian Zhang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2015	A	`conf`	A ultra-low-power FPGA based on monolithically integrated RRAMs. DATE Pierre-Emmanuel Gaillardon, Xifan Tang, Jury Sandrini, Maxime Thammasack, Somayyeh Rahimian Omam, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli
2015	B	`conf`	Accurate power analysis for near-Vt RRAM-based FPGA. FPL Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2015	—	`conf`	Exploiting Circuit Duality to Speed up SAT. ISVLSI Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Maciej J. Ciesielski, Giovanni De Micheli
2015	—	`conf`	Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. ACM Great Lakes Symposium on VLSI Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino, Luca Gaetano Amarù, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
2015	C	`conf`	FPGA-SPICE: A simulation-based power estimation framework for FPGAs. ICCD Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2015	A	`conf`	Fault modeling in controllable polarity silicon nanowire circuits. DATE Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2015	—	`conf`	Multiple Independent Gate FETs: How many gates do we need? ASP-DAC Luca Gaetano Amarù, Gage Hills, Pierre-Emmanuel Gaillardon, Subhasish Mitra, Giovanni De Micheli
2015	—	`conf`	NEM relay design with biconditional binary decision diagrams. NANOARCH Winston Haaswijk, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2015	J	`jnl`	New Logic Synthesis as Nanotechnology Enabler. Proc. IEEE Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Subhasish Mitra, Giovanni De Micheli
2015	—	`conf`	On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors. ISVLSI Hassan Ghasemzadeh, Pierre-Emmanuel Gaillardon, J. Zhang, Giovanni De Micheli, Ernesto Sánchez, Matteo Sonza Reorda
2015	C	`conf`	Reliable and high performance STT-MRAM architectures based on controllable-polarity devices. ICCD Kaveh Shamsi, Yu Bi, Yier Jin, Pierre-Emmanuel Gaillardon, Michael T. Niemier, Xiaobo Sharon Hu
2015	—	`conf`	Reversible Logic Synthesis via Biconditional Binary Decision Diagrams. ISMVL Anupam Chattopadhyay, Alessandro Littarru, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2015	A	`conf`	Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only). FPGA Pierre-Emmanuel Gaillardon, Gain Kim, Xifan Tang, Luca Gaetano Amarù, Giovanni De Micheli
2014	—	`conf`	3D technologies for reconfigurable architectures. ReCoSoC Fabien Clermidy, O. Turkyimaz, Olivier Billoint, Pierre-Emmanuel Gaillardon
2014	—	`conf`	A high-performance low-power near-Vt RRAM-based FPGA. FPT Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2014	A	`conf`	A new basic logic structure for data-path computation (abstract only). FPGA Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Giovanni De Micheli
2014	A	`conf`	Advanced system on a chip design based on controllable-polarity FETs. DATE Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Jian Zhang, Giovanni De Micheli
2014	A	`conf`	An efficient manipulation package for Biconditional Binary Decision Diagrams. DATE Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2014	J	`jnl`	Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form. IEEE J. Emerg. Sel. Topics Circuits Syst. Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2014	J	`jnl`	Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs. IEEE Trans. Circuits Syst. I Regul. Pap. Jian Zhang, Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2014	—	`conf`	Data compression via logic synthesis. ASP-DAC Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Andreas Burg, Giovanni De Micheli
2014	J	`jnl`	Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design. IEEE Trans. Circuits Syst. I Regul. Pap. Ibrahim Kazi, Pascal Andreas Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Yusuf Leblebici, Andreas Peter Burg, Giovanni De Micheli
2014	—	`conf`	Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection. NANOARCH Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Majid Yazdani, Giovanni De Micheli
2014	—	`conf`	Leveraging Emerging Technology for Hardware Security - Case Study on Silicon Nanowire FETs and Graphene SymFETs. ATS Yu Bi, Pierre-Emmanuel Gaillardon, Xiaobo Sharon Hu, Michael T. Niemier, Jiann-Shiun Yuan, Yier Jin
2014	C	`conf`	Majority Logic Synthesis for Spin Wave Technology. DSD Odysseas Zografos, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Praveen Raghavan, Giovanni De Micheli
2014	A*	`conf`	Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization. DAC Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2014	—	`conf`	Novel configurable logic block architecture exploiting controllable-polarity transistors. ReCoSoC Pierre-Emmanuel Gaillardon, Xifan Tang, Giovanni De Micheli
2014	C	`conf`	Novel grid-based power routing scheme for regular controllable-polarity FET arrangements. ISCAS Odysseas Zografos, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2014	B	`conf`	Pattern-based FPGA logic block and clustering algorithm. FPL Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2014	J	`jnl`	System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits. ACM J. Emerg. Technol. Comput. Syst. Shashikanth Bobba, Jie Zhang, Pierre-Emmanuel Gaillardon, H.-S. Philip Wong, Subhasish Mitra, Giovanni De Micheli
2014	C	`conf`	TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs. ISCAS Xifan Tang, Jian Zhang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2014	—	`conf`	Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis. ISVLSI Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Giovanni De Micheli
2013	C	`conf`	3.5-D integration: A case study. ISCAS Shashikanth Bobba, Pierre-Emmanuel Gaillardon, Ciprian Seiculescu, Vasilis F. Pavlidis, Giovanni De Micheli
2013	—	`conf`	A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write. NEWCAS Ibrahim Kazi, Pascal Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Andreas Burg, Giovanni De Micheli
2013	—	`conf`	A fast TCAD-based methodology for Variation analysis of emerging nano-devices. DFTS Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Majid Yazdani, Giovanni De Micheli
2013	A*	`conf`	BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition. DAC Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2013	A	`conf`	Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits. DATE Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2013	C	`conf`	Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs. ISCAS Jian Zhang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2013	—	`conf`	Efficient arithmetic logic gates using double-gate silicon nanowire FETs. NEWCAS Luca Arnani, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2013	—	`conf`	MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits. ASP-DAC Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2013	J	`jnl`	Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors. IEEE Trans. Circuits Syst. II Express Briefs Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Jian Zhang, Giovanni De Micheli
2013	—	`conf`	SATSoT: A methodology to map controllable-polarity devices on a regular fabric using SAT. NANOARCH Catherine Gasnier, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2013	C	`conf`	Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET. ISCAS Ogun Turkyilmaz, Fabien Clermidy, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2013	A*	`conf`	Towards structured ASICs using polarity-tunable Si nanowire transistors. DAC Pierre-Emmanuel Gaillardon, Michele De Marchi, Luca Gaetano Amarù, Shashikanth Bobba, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli
2013	A	`conf`	Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs. DATE Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Shashikanth Bobba, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli
2013	—	`conf`	Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. LATW Pierre-Emmanuel Gaillardon, Hassan Ghasemzadeh, Giovanni De Micheli
2012	J	`jnl`	3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst. Perrine Batude, Thomas Ernst, Julien Arcamone, Gregory Arndt, Perceval Coudrain, Pierre-Emmanuel Gaillardon
2012	C	`conf`	GMS: Generic memristive structure for non-volatile FPGAs. VLSI-SoC Pierre-Emmanuel Gaillardon, Davide Sacchetto, Shashikanth Bobba, Yusuf Leblebici, Giovanni De Micheli
2012	—	`conf`	Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors. NANOARCH Shashikanth Bobba, Pierre-Emmanuel Gaillardon, Jian Zhang, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli
2011	A*	`conf`	Can we go towards true 3-D architectures? DAC Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Paul-Henry Morel, Jean-Philippe Noël, Fabien Clermidy, Ian O'Connor
2011	C	`conf`	Evaluation of a crossbar multiplexer in a lithography-based nanowire technology. ISCAS Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Fabien Clermidy, Ian O'Connor
2011	J	`jnl`	Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method. ACM J. Emerg. Technol. Comput. Syst. Pierre-Emmanuel Gaillardon, Fabien Clermidy, Ian O'Connor, Junchen Liu, Maimouna Amadou, Gabriela Nicolescu
2011	—	`conf`	Ultra-fine grain FPGAs: A granularity study. NANOARCH Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Fabien Clermidy, Ian O'Connor
2011	—	`conf`	Using OxRRAM memories for improving communications of reconfigurable FPGA architectures. NANOARCH Santhosh Onkaraiah, Pierre-Emmanuel Gaillardon, Marina Reyboz, Fabien Clermidy, Jean-Michel Portal, Marc Bocquet, Christophe Muller
2010	—	`conf`	Emerging memory technologies for reconfigurable routing in FPGA architecture. ICECS Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Giovanni Betti Beneventi, Fabien Clermidy, Luca Perniola
2010	—	`conf`	Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics. ICECS Ian O'Connor, Kotb Jabeur, David Navarro, Nataliya Yakymets, Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Fabien Clermidy
2010	—	`conf`	Phase-change-memory-based storage elements for configurable logic. FPT Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Marina Reyboz, Giovanni Beneventi, Fabien Clermidy, Luca Perniola, Ian O'Connor
2010	—	`conf`	Reducing transistor count in clocked standard cells with ambipolar double-gate FETs. NANOARCH Kotb Jabeur, David Navarro, Ian O'Connor, Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Fabien Clermidy
2009	C	`conf`	Emerging Technologies and Nanoscale Computing Fabrics. VLSI-SoC Ian O'Connor, Junchen Liu, Kotb Jabeur, Nataliya Yakymets, Renaud Daviot, David Navarro, Pierre-Emmanuel Gaillardon, Fabien Clermidy, Maimouna Amadou, Gabriela Nicolescu
2009	—	`conf`	Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices. NANOARCH Pierre-Emmanuel Gaillardon, Fabien Clermidy, Ian O'Connor, Junchen Liu
2009	—	`conf`	Mapping method of reconfigurable cell matrices based on nanoscale devices using inter-stage fixed interconnection scheme. ICECS Pierre-Emmanuel Gaillardon, Fabien Clermidy, Ian O'Connor, Junchen Liu, Renaud Daviot
2009	—	`conf`	Reconfigurable nanoscale logic cells : a comparison study. ICECS Pierre-Emmanuel Gaillardon, Fabien Clermidy, Ian O'Connor, Renaud Daviot