Pierpaolo Palestri

48 papers C 4Journal 18Unranked 25
YearRankTypeTitle / Venue / Authors
2025 — conf
Design and Simulation of a 64 Gb/s PAM-4 Wireline Receiver in 22 nm CMOS.
PRIME
A. Cortiula, D. Scubla, S. Murra, Davide Menin, Andrea Bandiziol, Francesco Driussi, Pierpaolo Palestri
2025 — conf
Impact of Gate Metal Work Function on 1/f Noise in RMG MOSFETs.
IRPS
Ruben Asanovski, Hiroaki Arimura, J. Ganguly, Pierpaolo Palestri, Alexander Grill, Ben Kaczer, Naoto Horiguchi, Luca Selmi, Jacopo Franco
2024 J jnl
From Finite Element Simulations to Equivalent Circuit Models of Extracellular Neuronal Recording Systems Based on Planar and Mushroom Electrodes.
IEEE Trans. Biomed. Eng.
Federico Leva, Claudio Verardo, Pierpaolo Palestri, Luca Selmi
2023 J jnl
A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap.
Alessio Cortiula, Davide Menin, Andrea Bandiziol, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri
2023 — conf
Identification of Axon Bendings in Neurons by Multiphysics FEM Simulations of High-Density MEA Extracellular Recordings.
SENSORS
Federico Leva, Andrea Corna, Paul Werginz, Pierpaolo Palestri, Günter Zeck, Luca Selmi
2023 — conf
Mitigation of Electrical/Ionic Interference in Iontronic Neurostimulation/Neurosensing Platforms: A Simulation Study.
SENSORS
Jacopo Nicolini, Federico Leva, Pierpaolo Palestri, Luca Selmi
2022 — conf
Multiphysics Finite-Element Modeling of the Neuron/Electrode Electrodiffusive Interaction.
IEEE SENSORS
Federico Leva, Claudio Verardo, Leandro Julian Mele, Pierpaolo Palestri, Luca Selmi
2022 J jnl
Synchrotron Radiation Study of Gain, Noise, and Collection Efficiency of GaAs SAM-APDs with Staircase Structure.
Sensors
Matija Colja, Marco Cautero, Ralf-Hendrik Menk, Pierpaolo Palestri, Alessandra Gianoncelli, Matias Antonelli, Giorgio Biasiol, Simone Dal Zilio, Tereza Steinhartova, Camilla Nichetti, Fulvia Arfelli, Dario De Angelis, Francesco Driussi, Valentina Bonanni, Alessandro Pilotto, Gianluca Gariani, Sergio Carrato, Giuseppe Cautero
2021 J jnl
A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Hayate Okuhara, Ahmed Elnaqib, Martino Dazzi, Pierpaolo Palestri, Simone Benatti, Luca Benini, Davide Rossi
2021 J jnl
A Fully-Integrated 5mW, 0.8Gbps Energy-Efficient Chip-to-Chip Data Link for Ultra-Low-Power IoT End-Nodes in 65-nm CMOS.
CoRR
Hayate Okuhara, Ahmed Elnaqib, Martino Dazzi, Pierpaolo Palestri, Simone Benatti, Luca Benini, Davide Rossi
2021 J jnl
Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation.
IEEE Trans. Very Large Scale Integr. Syst.
Pierpaolo Palestri, Ahmed Elnaqib, Davide Menin, Klaid Shyti, Francesco Brandonisio, Andrea Bandiziol, Davide Rossi, Roberto Nonis
2021 J jnl
Sensitivity, Noise and Resolution in a BEOL-Modified Foundry-Made ISFET with Miniaturized Reference Electrode for Wearable Point-of-Care Applications.
Sensors
Francesco Bellando, Leandro Julian Mele, Pierpaolo Palestri, Junrui Zhang, Adrian Mihai Ionescu, Luca Selmi
2020 C conf
An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes.
ISCAS
Hayate Okuhara, Ahmed Elnaqib, Davide Rossi, Alfio Di Mauro, Philipp Mayer, Pierpaolo Palestri, Luca Benini
2020 J jnl
An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes.
CoRR
Hayate Okuhara, Ahmed Elnaqib, Davide Rossi, Alfio Di Mauro, Philipp Mayer, Pierpaolo Palestri, Luca Benini
2020 J jnl
Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Davide Menin, Andrea Bandiziol, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri
2020 — conf
Ultra-High Frequency (500 MHz) Capacitance Spectroscopy for Nanobiosensing.
IEEE SENSORS
Andrea Cossettini, Denis Brandalise, Pierpaolo Palestri, Alessandro Bertacchini, Michele Ramponi, Frans Widdershoven, Luca Benini, Luca Selmi
2019 — conf
A simple and fast tool for the modelling of inter-symbol interference and equalization in high-speed chip-to-chip interfaces.
MIPRO
Alessio Cortiula, Martino Dazzi, Mattia Marcon, Davide Menin, Marco Scapol, Andrea Bandiziol, Andrea Cristofoli, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri
2019 — conf
Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers.
APCCAS
Dylan D'Ampolo, Andrea Bandiziol, Davide Menin, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri
2018 J jnl
Design and Characterization of a 9.2-Gb/s Transceiver for Automotive Microcontroller Applications With 8-Taps FFE and 1-Tap Unrolled/4-Taps DFE.
IEEE Trans. Circuits Syst. II Express Briefs
Andrea Bandiziol, Werner Grollitsch, Giovanni Steffan, Roberto Nonis, Pierpaolo Palestri
2018 C conf
Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm.
ISCAS
Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Matteo Bassi, Roberto Nonis, Pierpaolo Palestri
2018 C conf
Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes.
ISCAS
Martino Dazzi, Pierpaolo Palestri, Davide Rossi, Andrea Bandiziol, Igor Loi, David E. Bellasi, Luca Benini
2017 — conf
Experimental characterization of the static noise margins of strained silicon complementary tunnel-FET SRAM.
ESSDERC
Gia Vinh Luong, Sebastiano Strangio, Andreas T. Tiedemann, Patric Bernardy, Stefan Trellenkamp, Pierpaolo Palestri, Siegfried Mantl, Qing-Tai Zhao
2016 — conf
Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers.
APCCAS
Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Roberto Nonis, Pierpaolo Palestri
2016 — conf
Design of a transmitter for high-speed serial interfaces in automotive micro-controller.
MIPRO
Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Roberto Nonis, Pierpaolo Palestri
2016 — conf
Impact of device geometry of the fin Electron-Hole Bilayer Tunnel FET.
ESSDERC
Cem Alper, Jose L. Padilla, Pierpaolo Palestri, Adrian M. Ionescu
2016 — conf
Performance study of strained III-V materials for ultra-thin body transistor applications.
ESSDERC
Martin Rau, Troels Markussen, Enrico Caruso, David Esseni, Elena Gnani, Antonio Gnudi, Petr A. Khomyakov, Mathieu Luisier, Patrik Osgnach, Pierpaolo Palestri, Susanna Reggiani, Andreas Schenk, Luca Selmi, Kurt Stokbro
2015 J jnl
Design and implementation of switched coil LC-VCOs in the GHz range using the self-inductance technique.
Int. J. Circuit Theory Appl.
Federico Cernoia, Davide Ponton, Pierpaolo Palestri, Peter Thurner, Nicola Da Dalt, Giulio Cecco, Luca Selmi
2015 — conf
Design, characterization and signal integrity analysis of a 2.5 Gb/s High-Speed Serial Interface for automotive applications overarching the chip/PCB wall.
RTSI
Andrea Cossettini, Andrea Cristofoli, Werner Grollitsch, Lino Alves, Roberto Nonis, Luca Della Ricca, Pierpaolo Palestri, Luca Selmi
2015 — conf
Improved surface roughness modeling and mobility projections in thin film MOSFETs.
ESSDERC
O. Badami, Enrico Caruso, Daniel Lizzit, David Esseni, Pierpaolo Palestri, Luca Selmi
2015 — conf
State-of-the-art semi-classical Monte Carlo method for carrier transport in nanoscale transistors.
MIPRO
Pierpaolo Palestri, Enrico Caruso, Francesco Driussi, David Esseni, Daniel Lizzit, Patrik Osgnach, Stefano Venica, Luca Selmi
2014 — conf
Analysis of TFET based 6T SRAM cells implemented with state of the art silicon nanowires.
ESSDERC
Sebastiano Strangio, Pierpaolo Palestri, David Esseni, Luca Selmi, Felice Crupi
2014 — conf
Graphene base transistors with optimized emitter and dielectrics.
MIPRO
Stefano Venica, Francesco Driussi, Pierpaolo Palestri, Luca Selmi
2014 — conf
Two dimensional quantum mechanical simulation of low dimensional tunneling devices.
ESSDERC
Cem Alper, Pierpaolo Palestri, Livio Lattanzio, Jose L. Padilla, Adrian M. Ionescu
2013 — conf
On the optimization of SiGe and III-V compound hetero-junction Tunnel FET devices.
ESSDERC
Alberto Revelant, Pierpaolo Palestri, Patrik Osgnach, Daniel Lizzit, Luca Selmi
2013 — conf
On the response of nanoelectrode capacitive biosensors to DNA and PNA strands.
IWASI
Federico Pittino, Federico Passerini, Pierpaolo Palestri, Luca Selmi, Frans Widdershoven
2012 — conf
A Multi-Subband Monte Carlo study of electron transport in strained SiGe n-type FinFETs.
ESSDERC
Daniel Lizzit, Pierpaolo Palestri, David Esseni, Francesco Conzatti, Luca Selmi
2012 J jnl
Microscopic scale characterization and modeling of transistor degradation under HC stress.
Microelectron. Reliab.
Yoann Mamy Randriamihaja, Vincent Huard, Xavier Federspiel, Alban Zaka, Pierpaolo Palestri, Denis Rideau, David Roy, Alain Bravaix
2011 J jnl
LC-VCO in the 3.3- to 4-GHz Band Implemented in 32-nm Low-Power CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs
Davide Ponton, Gerhard Knoblinger, Andreas Roithmeier, Federico Cernoia, Marc Tiebout, Michael Fulde, Pierpaolo Palestri
2010 J jnl
A numerical model for the oscillation frequency, the amplitude and the phase-noise of MOS-current-mode-logic ring oscillators.
Int. J. Circuit Theory Appl.
Michele Nocente, Donald Fontanelli, Pierpaolo Palestri, Roberto Nonis, David Esseni, Luca Selmi
2009 — conf
Assessment of the impact of technology scaling on the performance of LC-VCOs.
ESSCIRC
Davide Ponton, Gerhard Knoblinger, Andreas Roithmeier, Marc Tiebout, Michael Fulde, Pierpaolo Palestri
2009 J jnl
Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices.
IEEE Trans. Circuits Syst. I Regul. Pap.
Davide Ponton, Pierpaolo Palestri, David Esseni, Luca Selmi, Marc Tiebout, Bertrand Parvais, Domagoj Siprak, Gerhard Knoblinger
2008 J jnl
Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Luca Bizjak, Nicola Da Dalt, Peter Thurner, Roberto Nonis, Pierpaolo Palestri, Luca Selmi
2008 C conf
Design of UWB LNA in 45nm CMOS technology: Planar bulk vs. FinFET.
ISCAS
Davide Ponton, Pierpaolo Palestri, David Esseni, Luca Selmi, Marc Tiebout, Bertrand Parvais, Gerhard Knoblinger
2007 J jnl
A Design Methodology for MOS Current-Mode Logic Frequency Dividers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Roberto Nonis, Enzo Palumbo, Pierpaolo Palestri, Luca Selmi
2007 — conf
The Monte Carlo approach to transport modeling in deca-nanometer MOSFETs.
ESSCIRC
Enrico Sangiorgi, Pierpaolo Palestri, David Esseni, Claudio Fiegna, Luca Selmi
2005 J jnl
Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture.
IEEE J. Solid State Circuits
Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri, Luca Selmi
2005 — —
Monte-Carlo simulations of hot-carrier effectes and photon-emission in MOS devices.
Pierpaolo Palestri
2004 — conf
Modeling, design and characterization of a new low jitter analog dual tuning LC-VCO PLL architecture.
ISCAS (4)
Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri, Luca Selmi