Pierangelo Terreni

35 papers A* 1C 4Misc 1Journal 16Unranked 13

Year	Rank	Type	Title / Venue / Authors
2014	—	`conf`	A Real-Time FPGA-based Solution for Binary Image Thinning. ApplePies Daniele Davalle, Berardino Carnevale, Sergio Saponara, Luca Fanucci, Pierangelo Terreni
2012	C	`conf`	Hardware building blocks of a hierarchical battery management system for a fuel cell HEV. IECON Federico Baronti, Gabriele Fantechi, Roberto Roncella, Roberto Saletti, Pierangelo Terreni
2011	J	`jnl`	Sensor Modeling, Low-Complexity Fusion Algorithms, and Mixed-Signal IC Prototyping for Gas Measures in Low-Emission Vehicles. IEEE Trans. Instrum. Meas. Sergio Saponara, Esa Petri, Luca Fanucci, Pierangelo Terreni
2010	J	`jnl`	Mixed-Signal Architectures for High-Efficiency and Low-Distortion Digital Audio Processing and Power Amplification. EURASIP J. Embed. Syst. Sergio Saponara, Pierangelo Terreni
2009	—	`conf`	Sensor modeling and data fusion for a safety warning system in hydrogen-based vehicles. ROSE Sergio Saponara, Alessandro Forconi, Pierangelo Terreni
2009	—	`conf`	Sensor modeling and fusion algorithms for NOx measures towards zero emissions vehicles. ROSE Antonio Giampà, Esa Petri, Sergio Saponara, Pierangelo Terreni
2009	—	`conf`	Smart transducer interface in embedded systems for networked sensors based on the emerging IEEE 1451 Standard: H2 Detection Case Study. WISES Sergio Saponara, Esa Petri, Luca Fanucci, Pierangelo Terreni
2008	J	`jnl`	Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems. IEICE Trans. Electron. Nicola E. L'Insalata, Sergio Saponara, Luca Fanucci, Pierangelo Terreni
2008	J	`jnl`	Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. Pierluigi Nuzzo, Fernando De Bernardinis, Pierangelo Terreni, Geert Van der Plas
2007	J	`jnl`	Architectural-Level Power Optimization of Microcontroller Cores in Embedded Systems. IEEE Trans. Ind. Electron. Sergio Saponara, Luca Fanucci, Pierangelo Terreni
2007	C	`conf`	Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM Systems. DSD Nicola E. L'Insalata, Sergio Saponara, Luca Fanucci, Pierangelo Terreni
2006	A*	`conf`	A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBW. DAC Pierluigi Nuzzo, Geert Van der Plas, Fernando De Bernardinis, Liesbet Van der Perre, Bert Gyselinckx, Pierangelo Terreni
2006	—	`conf`	Mixed-signal design of a digital input power amplifier for automotive audio applications. DATE Designers' Forum Sergio Saponara, Pierangelo Terreni
2006	—	`conf`	Oversampled and Noise-Shaped Pulse-Width Modulator for High-Fidelity Digital Audio Amplifier. ICECS Sergio Saponara, Luca Fanucci, Pierangelo Terreni
2005	—	`conf`	Enriching an analog platform for analog-to-digital converter design. ISCAS (2) Fernando De Bernardinis, Pierluigi Nuzzo, Pierangelo Terreni, Alberto L. Sangiovanni-Vincentelli
2005	J	`jnl`	Self-Adaptive Algorithmic/Architectural Design for Real-Time, Low-Power Video Systems. IEICE Trans. Inf. Syst. Luca Fanucci, Sergio Saponara, Massimiliano Melani, Pierangelo Terreni
2004	—	`conf`	Adaptive algorithm for fast motion estimation in H.264/MPEG-4 AVC. EUSIPCO Sergio Saponara, Massimiliano Melani, Luca Fanucci, Pierangelo Terreni
2004	—	`conf`	Context-Aware Algorithmic/Architectural Solutions for Real-time Embedded Video Systems. WISES Sergio Saponara, Luca Fanucci, Pierangelo Terreni
2004	J	`jnl`	Design of a Low-Power VLSI Macrocell for Nonlinear Adaptive Video Noise Reduction. EURASIP J. Adv. Signal Process. Sergio Saponara, Luca Fanucci, Pierangelo Terreni
2003	—	`conf`	A QoS Internet Protocol Scheduler on the IXP1200 Network Platform. IWSOC Fernando De Bernardinis, Luca Fanucci, Tommaso Ramacciotti, Pierangelo Terreni
2002	J	`jnl`	FAST: FFT ASIC automated synthesis. Integr. Luca Fanucci, Massimiliano Forliti, Pierangelo Terreni
2002	—	`conf`	VLSI design of a routing switch for the SpaceWire serial link standard. ICECS Luca Fanucci, Alessandro Renieri, Pierangelo Terreni
1999	J	`jnl`	An efficient VLSI architecture for real-time additive synthesis of musical signals. IEEE Trans. Very Large Scale Integr. Syst. Fernando De Bernardinis, Roberto Roncella, Roberto Saletti, Pierangelo Terreni, Graziano Bertini
1998	J	`jnl`	Multihit multichannel time-to-digital converter with ±1% differential nonlinearity and near optimal time resolution. IEEE J. Solid State Circuits Pietro Andreani, Franco Bigongiari, Roberto Roncella, Roberto Saletti, Pierangelo Terreni, Adriano Bigongiari, Maurizio Lippi
1997	J	`jnl`	A pyramid vector quantizer chip for HDTV applications. Eur. Trans. Telecommun. Fabio Bellifemine, Romualdo Picco, Roberto Roncella, Roberto Saletti, Pierangelo Terreni
1997	Misc	`conf`	A single-chip 1, 200 sinusoid real-time generator for additive synthesis of musical signals. ICASSP Fernando De Bernardinis, Roberto Roncella, Roberto Saletti, Pierangelo Terreni, Graziano Bertini
1997	—	`conf`	On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic. ASYNC Riccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni
1997	—	`conf`	Useful Application of CMOS Ternary Logic to the Realisation of Asynchronous Circuits. ISMVL Riccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni
1993	J	`jnl`	70-MHz 2- mu m CMOS bit-level systolic array median filter. IEEE J. Solid State Circuits Roberto Roncella, Roberto Saletti, Pierangelo Terreni
1993	C	`conf`	Conditions for the existence and uniqueness of DC solutions of networks containing nonlinear opamps with ideal model. ISCAS Maurizio Ciampa, Pierangelo Terreni, Mario Poletti
1993	J	`jnl`	Linear networks and systems depending polynomially on parameters: Stability for large values subject to tolerance errors. Int. J. Circuit Theory Appl. Maurizio Ciampa, Mario Poletti, Pierangelo Terreni
1993	C	`conf`	Linear networks and systems polynomially depending on parameters: Behaviour of the solutions for large and small values. ISCAS Maurizio Ciampa, Pierangelo Terreni, Mario Poletti
1992	J	`jnl`	ASIC-based acoustic echo-canceller board for VME bus. Eur. Trans. Telecommun. Franco Maloberti, Guido Torelli, Claudio Panini, Mauro Troiani, Roberto Roncella, Pierangelo Terreni, Cristiano Toncelli, Roberto Saletti
1992	J	`jnl`	Single-chip adaptive FIR filter for acoustic echo canceller board. Signal Process. Roberto Roncella, Roberto Saletti, Pierangelo Terreni, Cristiano Toncelli
1990	J	`jnl`	An example of a new VLSI design style based on systolic macrocells: A high-speed single-chip transversal filter for signal processing applications. Eur. Trans. Telecommun. Roberto Roncella, Roberto Saletti, Pierangelo Terreni