Pi-Feng Chiu - RankMe

28 papers C 4Journal 11Unranked 12

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI. IEEE Trans. Very Large Scale Integr. Syst. John Charles Wright, Colin Schmidt, Ben Keller, Daniel Palmer Dabbelt, Jaehwa Kwak, Vighnesh Iyer, Nandish Mehta, Pi-Feng Chiu, Stevo Bailey, Krste Asanovic, Borivoje Nikolic
2020	C	`conf`	A Mott Insulator-Based Oscillator Circuit for Reservoir Computing. ISCAS Wen Ma, Tyler Hennen, Martin Lueker-Boden, Rick Galbraith, Jonas Goode, Won Ho Choi, Pi-Feng Chiu, Jonathan A. J. Rupp, Dirk J. Wouters, Rainer Waser, Daniel Bedau
2020	C	`conf`	An In-Flash Binary Neural Network Accelerator with SLC NAND Flash Array. ISCAS Won Ho Choi, Pi-Feng Chiu, Wen Ma, Gertjan Hemink, Tung Thanh Hoang, Martin Lueker-Boden, Zvonimir Bandic
2020	J	`jnl`	Non-Volatile Memory Array Based Quantization- and Noise-Resilient LSTM Neural Networks. CoRR Wen Ma, Pi-Feng Chiu, Won Ho Choi, Minghai Qin, Daniel Bedau, Martin Lueker-Boden
2019	C	`conf`	A Binarized Neural Network Accelerator with Differential Crosspoint Memristor Array for Energy-Efficient MAC Operations. ISCAS Pi-Feng Chiu, Won Ho Choi, Wen Ma, Minghai Qin, Martin Lueker-Boden
2019	J	`jnl`	BROOM: An Open-Source Out-of-Order Processor With Resilient Low-Voltage Operation in 28-nm CMOS. IEEE Micro Christopher Celio, Pi-Feng Chiu, Krste Asanovic, Borivoje Nikolic, David A. Patterson
2019	—	`conf`	Non-Volatile Memory Array Based Quantization- and Noise-Resilient LSTM Neural Networks. ICRC Wen Ma, Pi-Feng Chiu, Won Ho Choi, Minghai Qin, Daniel Bedau, Martin Lueker-Boden
2018	—	`conf`	An Out-of-Order RISC-V Processor with Resilient Low-Voltage Operation in 28NM CMOS. VLSI Circuits Pi-Feng Chiu, Christopher Celio, Krste Asanovic, David A. Patterson, Borivoje Nikolic
2018	—	`—`	Bottom-up Memory Design Techniques for Energy-Efficient and Resilient Computing Pi-Feng Chiu
2018	C	`conf`	Improving Noise Tolerance of Hardware Accelerated Artificial Neural Networks. ICMLA Wen Ma, Minghai Qin, Won Ho Choi, Pi-Feng Chiu, Martin Lueker-Boden
2017	J	`jnl`	A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI. IEEE J. Solid State Circuits Ben Keller, Martin Cochet, Brian Zimmer, Jaehwa Kwak, Alberto Puggelli, Yunsup Lee, Milovan Blagojevic, Stevo Bailey, Pi-Feng Chiu, Daniel Palmer Dabbelt, Colin Schmidt, Elad Alon, Krste Asanovic, Borivoje Nikolic
2017	J	`jnl`	Reprogrammable Redundancy for SRAM-Based Cache V IEEE J. Solid State Circuits Brian Zimmer, Pi-Feng Chiu, Borivoje Nikolic, Krste Asanovic
2016	J	`jnl`	A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. IEEE J. Solid State Circuits Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Steven Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic
2016	—	`conf`	A double-tail sense amplifier for low-voltage SRAM in 28nm technology. A-SSCC Pi-Feng Chiu, Brian Zimmer, Borivoje Nikolic
2016	J	`jnl`	An Agile Approach to Building RISC-V Microprocessors. IEEE Micro Yunsup Lee, Andrew Waterman, Henry Cook, Brian Zimmer, Ben Keller, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Rimas Avizienis, Brian C. Richards, Jonathan Bachrach, David A. Patterson, Elad Alon, Bora Nikolic, Krste Asanovic
2016	—	`conf`	Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor. A-SSCC Brian Zimmer, Pi-Feng Chiu, Borivoje Nikolic, Krste Asanovic
2016	—	`conf`	Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC. ESSCIRC Ben Keller, Martin Cochet, Brian Zimmer, Yunsup Lee, Milovan Blagojevic, Jaehwa Kwak, Alberto Puggelli, Stevo Bailey, Pi-Feng Chiu, Daniel Palmer Dabbelt, Colin Schmidt, Elad Alon, Krste Asanovic, Borivoje Nikolic
2015	J	`jnl`	A Differential 2R Crosspoint RRAM Array With Zero Standby Current. IEEE Trans. Circuits Syst. II Express Briefs Pi-Feng Chiu, Borivoje Nikolic
2015	—	`conf`	A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. VLSIC Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic
2015	—	`conf`	Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. Hot Chips Symposium Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Henry Cook, Rimas Avizienis, Brian C. Richards, Elad Alon, Borivoje Nikolic, Krste Asanovic
2013	J	`jnl`	A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes. IEEE J. Solid State Circuits Meng-Fan Chang, Shyh-Shyuan Sheu, Ku-Feng Lin, Che-Wei Wu, Chia-Chen Kuo, Pi-Feng Chiu, Yih-Shan Yang, Yu-Sheng Chen, Heng-Yuan Lee, Chen-Hsin Lien, Frederick T. Chen, Keng-Li Su, Tzu-Kun Ku, Ming-Jer Kao, Ming-Jinn Tsai
2012	—	`conf`	Endurance-aware circuit designs of nonvolatile logic and nonvolatile sram using resistive memory (memristor) device. ASP-DAC Meng-Fan Chang, Ching-Hao Chuang, Min-Ping Chen, Lai-Fu Chen, Hiroyuki Yamauchi, Pi-Feng Chiu, Shyh-Shyuan Sheu
2012	J	`jnl`	Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications. IEEE J. Solid State Circuits Pi-Feng Chiu, Meng-Fan Chang, Che-Wei Wu, Ching-Hao Chuang, Shyh-Shyuan Sheu, Yu-Sheng Chen, Ming-Jinn Tsai
2011	—	`conf`	A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. ISSCC Shyh-Shyuan Sheu, Meng-Fan Chang, Ku-Feng Lin, Che-Wei Wu, Yu-Sheng Chen, Pi-Feng Chiu, Chia-Chen Kuo, Yih-Shan Yang, Pei-Chia Chiang, Wen-Pin Lin, Che-He Lin, Heng-Yuan Lee, Peiyi Gu, Sumin Wang, Frederick T. Chen, Keng-Li Su, Chen-Hsin Lien, Kuo-Hsing Cheng, Hsin-Tun Wu, Tzu-Kun Ku, Ming-Jer Kao, Ming-Jinn Tsai
2011	—	`conf`	Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM). ASICON Meng-Fan Chang, Pi-Feng Chiu, Wei-Cheng Wu, Ching-Hao Chuang, Shyh-Shyuan Sheu
2011	—	`conf`	Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC. ASP-DAC Meng-Fan Chang, Pi-Feng Chiu, Shyh-Shyuan Sheu
2010	—	`conf`	A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications. ISSCC Meng-Fan Chang, Shu-Meng Yang, Chih-Wei Liang, Chih-Chyuang Chiang, Pi-Feng Chiu, Ku-Feng Lin, Yuan-Hua Chu, Wen-Chin Wu, Hiroyuki Yamauchi
2010	J	`jnl`	Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements. IEEE J. Solid State Circuits Meng-Fan Chang, Shu-Meng Yang, Chih-Wei Liang, Chih-Chyuang Chiang, Pi-Feng Chiu, Ku-Feng Lin