Phillip J. Restle

53 papers A* 3A 4C 1Misc 1Journal 21Unranked 23

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Dynamic Guardband Features of the IBM z17 System. IEEE J. Solid State Circuits Tobias Webel, Phillip J. Restle, Ramon Bertran, Alper Buyuktosunoglu, Sean M. Carey, Alejandro Cook, Karl Anderson, Michael Romain, Thomas Strach, Pradeep Bhadravati Parashurama, Aishwarya Tadkase, Rahman Abber Tahir, Luke Jenkins, Kevin Low, Eberhard Engler
2025	—	`conf`	8.1 Dynamic Guard-Band Features of the IBM zNext System. ISSCC Tobias Webel, Phillip J. Restle, Ramon Bertran, Alper Buyuktosunoglu, Sean M. Carey, Alejandro Cook, Karl Anderson, Michael Romain, Thomas Strach, Pradeep Bhadravati Parashurama, Aishwarya Tadkase, Rahman Abber Tahir, Luke Jenkins, Kevin Low, Eberhard Engler
2023	J	`jnl`	Deterministic Frequency and Voltage Enhancements on the POWER10 Processor. IEEE J. Solid State Circuits Brian T. Vanderpool, Phillip J. Restle, Eric Fluhr, Gregory S. Still, Francesco A. Campisano, Ian Charmichael, Eric Marz, Rahul Batra, Richard L. Willaman
2022	—	`conf`	Deterministic Frequency Boost and Voltage Enhancements on the POWER10 ISSCC Brian T. Vanderpool, Phillip J. Restle, Eric J. Fluhr, Gregory S. Still, Frank Campisano, Ian Carmichael, Eric Marz, Rahul Batra, Richard L. Willaman
2019	J	`jnl`	IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems. IEEE J. Solid State Circuits Christopher J. Berry, David Wolpert, Christos Vezyrtzis, Richard F. Rizzolo, Sean M. Carey, Yaniv Maroz, Hunter F. Shi, Dureseti Chidambarrao, Christian Jacobi, Anthony Saporito, Thomas Strach, Alper Buyuktosunoglu, Preetham Lobo, Pierce Chuang, Pawel Owczarczyk, Ramon Bertran, Tobias Webel, Phillip J. Restle
2018	—	`conf`	Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor. ISSCC Christos Vezyrtzis, Thomas Strach, Pierce I-Jen Chuang, Preetham Lobo, Richard F. Rizzolo, Tobias Webel, Pawel Owczarczyk, Alper Buyuktosunoglu, Ramon Bertran, David T. Hui, Susan M. Eickhoff, Michael S. Floyd, Gerard Salem, Sean M. Carey, Stelios G. Tsapepas, Phillip J. Restle
2018	—	`conf`	EE5: Lessons learned - Great circuits that didn't work - (Oops, if only i had known!). ISSCC Phillip J. Restle, Kostas Doris, Vivek De, Paul Ferguson
2018	—	`conf`	Session 7 overview: Neuromorphic, clocking and security circuits: Digital circuits subcommittee. ISSCC Youngmin Shin, Phillip J. Restle, Edith Beigné
2018	J	`jnl`	The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. IEEE J. Solid State Circuits Christopher J. Gonzalez, Michael S. Floyd, Eric Fluhr, Phillip J. Restle, Daniel Dreps, Michael A. Sperling, Rahul M. Rao, David Hogenmiller, Christos Vezyrtzis, Pierce Chuang, Daniel Lewis, Ricardo Escobar, Vinod Ramadurai, Ryan Kruse, Juergen Pille, Ryan Nett, Pawel Owczarczyk, Joshua Friedrich, Jose Paredes, Timothy Diemoz, Md. Saiful Islam, Donald W. Plass, Paul Muench
2017	—	`conf`	26.2 Power supply noise in a 22nm z13™ microprocessor. ISSCC Pierce I-Jen Chuang, Christos Vezyrtzis, Divya Pathak, Richard F. Rizzolo, Tobias Webel, Thomas Strach, Otto A. Torreiter, Preetham Lobo, Alper Buyuktosunoglu, Ramon Bertran, Michael S. Floyd, Malcolm S. Ware, Gerard Salem, Sean M. Carey, Phillip J. Restle
2017	—	`conf`	26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection. ISSCC Michael S. Floyd, Phillip J. Restle, Michael A. Sperling, Pawel Owczarczyk, Eric J. Fluhr, Joshua Friedrich, Paul Muench, Timothy Diemoz, Pierce Chuang, Christos Vezyrtzis
2016	—	`conf`	Thermal analysis of multi-layer functional 3D logic stacks. 3DIC Michael Scheuermann, Shurong Tian, Raphael Robertazzi, Matthew R. Wordeman, C. Bergeron, H. Jacobson, Phillip J. Restle, Joel Silberman, Christy Tyberg
2015	J	`jnl`	IBM POWER8 circuit design and energy optimization. IBM J. Res. Dev. Victor V. Zyuban, Joshua Friedrich, Daniel M. Dreps, Jürgen Pille, Donald W. Plass, Phillip J. Restle, Zeynep Toprak Deniz, Matthew M. Ziegler, Sam G. Chu, Md. Saiful Islam, James D. Warnock, Bob Philhower, Rahul M. Rao, Gregory S. Still, David Shan, Eric Fluhr, Jose Paredes, Dieter F. Wendel, Christopher J. Gonzalez, D. Hogenmiller, Ruchir Puri, Scott A. Taylor, Stephen D. Posluszny
2015	—	`conf`	Resonant clock mega-mesh for the IBM z13 VLSIC David Shan, Phillip J. Restle, Doug Malone, Robert A. Groves, Eric Lai, Michael Koch, Jason Hibbeler, Yong Kim, Christos Vezyrtzis, Jan Feder, David Hogenmiller, Thomas J. Bucelot
2015	J	`jnl`	The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. IEEE J. Solid State Circuits Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban
2014	—	`conf`	5.1 POWER8 ISSCC Eric J. Fluhr, Joshua Friedrich, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, Allen Hall, David Hogenmiller, Frank Malgioglio, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Ruchir Puri, Phillip J. Restle, David Shan, Kevin Stawiasz, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler
2014	—	`conf`	5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8 ISSCC Phillip J. Restle, David Shan, David Hogenmiller, Yong Kim, Alan J. Drake, Jason Hibbeler, Thomas J. Bucelot, Gregory S. Still, Keith A. Jenkins, Joshua Friedrich
2014	—	`conf`	Optimization and modeling of resonant clocking inductors for the POWER8 CICC Robert A. Groves, Phillip J. Restle, Alan J. Drake, David Shan, Michael G. R. Thomson
2014	—	`conf`	Pacman: driving nonuniform clock grid loads for low-skew robust clock network. SLIP Nancy Y. Zhou, Phillip J. Restle, Joseph N. Palumbo, Joseph N. Kozhaya, Haifeng Qian, Zhuo Li, Charles J. Alpert, Cliff C. N. Sze
2014	—	`conf`	The POWER8 ICICDT Joshua Friedrich, Hung Q. Le, William J. Starke, Jeff Stuecheli, Balaram Sinharoy, Eric J. Fluhr, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, David Hogenmiller, Frank Malgioglio, Ryan Nett, Ruchir Puri, Phillip J. Restle, David Shan, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler, Dave W. Victor
2013	Misc	`conf`	On-chip circuit for measuring multi-GHz clock signal waveforms. VTS Keith A. Jenkins, Phillip J. Restle, P. Z. Wang, D. Hogenmiller, David W. Boerstler, Thomas J. Bucelot
2012	—	`conf`	A shorted global clock design for multi-GHz 3D stacked chips. VLSIC Liang-Teck Pang, Phillip J. Restle, Matthew R. Wordeman, Joel A. Silberman, Robert L. Franch, Gary W. Maier
2012	J	`jnl`	Subtractive Router for Tree-Driven-Grid Clocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haifeng Qian, Phillip J. Restle, Joseph N. Kozhaya, Clifford L. Gunion
2011	A	`conf`	Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus. ICCAD Joseph N. Kozhaya, Phillip J. Restle, Haifeng Qian
2011	J	`jnl`	POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. IEEE J. Solid State Circuits Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott A. Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban
2009	J	`jnl`	A Resonant Global Clock Distribution for the Cell Broadband Engine Processor. IEEE J. Solid State Circuits Steven C. Chan, Phillip J. Restle, Thomas J. Bucelot, John S. Liberty, Stephen Weitzel, John M. Keaty, Brian K. Flachs, Richard Volant, Peter Kapusta, Jeffrey S. Zimmerman
2009	—	`conf`	Ispd2009 clock network synthesis contest. ISPD Cliff N. Sze, Phillip J. Restle, Gi-Joon Nam, Charles J. Alpert
2008	—	`conf`	A Resonant Global Clock Distribution for the Cell Broadband-Engine Processor. ISSCC Steven C. Chan, Phillip J. Restle, Thomas J. Bucelot, Steve Weitzel, John M. Keaty, John S. Liberty, Brian K. Flachs, Richard Volant, Peter Kapusta, Jeffrey S. Zimmerman
2008	A	`conf`	On-chip Timing Uncertainty Measurements on IBM Microprocessors. ITC Robert L. Franch, Phillip J. Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, Gerard Salem
2007	—	`conf`	Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor. ISSCC Norman K. James, Phillip J. Restle, Joshua Friedrich, Bill Huott, Bradley D. McCredie
2007	J	`jnl`	IBM POWER6 microprocessor physical design and design methodology. IBM J. Res. Dev. Rex Berridge, Robert M. Averill III, Arnold E. Barish, Michael A. Bowen, Peter J. Camporese, Jack DiLullo, Peter E. Dudley, Joachim Keinert, David W. Lewis, Robert D. Morel, Thomas E. Rosser, Nicole S. Schwartz, Philip Shephard, Howard H. Smith, Dave Thomas, Phillip J. Restle, John R. Ripley, Stephen L. Runyon, Patrick M. Williams
2007	A	`conf`	On-chip timing uncertainty measurements on IBM microprocessors. ITC Robert L. Franch, Phillip J. Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, Gerard Salem
2006	—	`conf`	A 5GHz Duty-Cycle Correcting Clock Distribution Network for the POWER6 Microprocessor. ISSCC Michael G. R. Thomson, Phillip J. Restle, Norman K. James
2006	J	`jnl`	Distributed Differential Oscillators for Global Clock Networks. IEEE J. Solid State Circuits Steven C. Chan, Kenneth L. Shepard, Phillip J. Restle
2005	—	`conf`	Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. ACM Great Lakes Symposium on VLSI Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip J. Restle, Mary Yvonne Lanzerotti
2005	—	`conf`	New Prospects for Clocking Synchronous and Quasi-Asynchronous Systems. ASYNC Phillip J. Restle, Kenneth L. Shepard
2005	J	`jnl`	Uniform-phase uniform-amplitude resonant-load global clock distributions. IEEE J. Solid State Circuits Steven C. Chan, Kenneth L. Shepard, Phillip J. Restle
2004	A*	`conf`	Design and implementation of the POWER5 microprocessor. DAC Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam G. Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip J. Restle, Ronald N. Kalla, Joseph McGill, J. Steve Dodson
2003	C	`conf`	Design of Resonant Global Clock Distributions. ICCD Steven C. Chan, Kenneth L. Shepard, Phillip J. Restle
2003	J	`jnl`	Loop-based interconnect modeling and optimization approach for multigigahertz clock network design. IEEE J. Solid State Circuits Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King, Chenming Hu
2002	—	`conf`	Loop-based interconnect modeling and optimization approach for multi-GHz clock network design. CICC Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King
2002	J	`jnl`	The circuit and physical design of the POWER4 microprocessor. IBM J. Res. Dev. James D. Warnock, John M. Keaty, John G. Petrovick, Joachim G. Clabes, Charles J. Kircher, Byron Krauter, Phillip J. Restle, Brian A. Zoric, Carl J. Anderson
2001	J	`jnl`	A clock distribution network for microprocessors. IEEE J. Solid State Circuits Phillip J. Restle, Timothy G. McNamara, David A. Webber, Peter J. Camporese, Kwok F. Eng, Keith A. Jenkins, David H. Allen, Michael J. Rohn, Michael P. Quaranta, David W. Boerstler, Charles J. Alpert, Craig A. Carter, Roger N. Bailey, John G. Petrovick, Byron L. Krauter, Bradley D. McCredie
2001	J	`jnl`	Full-wave PEEC time-domain method for the modeling of on-chipinterconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Phillip J. Restle, Albert E. Ruehli, Steven G. Walker, George Papadopoulos
2001	—	`conf`	Multi-GHz interconnect effects in microprocessors. ISPD Phillip J. Restle, Albert E. Ruehli, Steven G. Walker
2001	J	`jnl`	On-chip wiring design challenges for gigahertz operation. Proc. IEEE Alina Deutsch, Paul W. Coteus, Gerard V. Kopcsay, Howard H. Smith, Christopher W. Surovic, Byron Krauter, Daniel C. Edelstein, Phillip J. Restle
2001	A*	`conf`	Technical Visualizations in VLSI Design. DAC Phillip J. Restle
1999	A*	`conf`	Dealing with Inductance in High-Speed Chip Design. DAC Phillip J. Restle, Albert E. Ruehli, Steven G. Walker
1998	A	`conf`	Interconnect in high speed designs: problems, methodologies and tools. ICCAD Phillip J. Restle, Joel R. Phillips, Ibrahim M. Elfadel
1998	J	`jnl`	Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor. IEEE J. Solid State Circuits Phillip J. Restle, Keith A. Jenkins, Alina Deutsch, Peter W. Cook
1997	J	`jnl`	A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders. IEEE J. Solid State Circuits Charles F. Webb, Carl J. Anderson, Leon J. Sigal, Kenneth L. Shepard, John S. Liptay, James D. Warnock, Brian W. Curran, Barry Krumm, Mark D. Mayo, Peter J. Camporese, Eric M. Schwarz, Mark S. Farrell, Phillip J. Restle, Robert M. Averill III, Timothy J. Slegel, William V. Huott, Yuen H. Chan, Bruce Wile, Thao N. Nguyen, Philip G. Emma, Daniel K. Beece, Ching-Te Chuang, Cyril Price
1989	J	`jnl`	A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces. IEEE J. Solid State Circuits Terry I. Chappell, Stanley E. Schuster, Barbara A. Chappell, James W. Allan, Jack Y.-C. Sun, Stephen P. Klepner, Robert L. Franch, Paul F. Greier, Phillip J. Restle
1988	J	`jnl`	Fast CMOS ECL receivers with 100-mV worst-case sensitivity. IEEE J. Solid State Circuits Barbara A. Chappell, Terry I. Chappell, Stanley E. Schuster, Hermann M. Segmuller, James W. Allan, Robert L. Franch, Phillip J. Restle