Phillip H. Jones

74 papers A 1B 7C 14Misc 5Journal 17Unranked 29

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	MLTL Multi-type: A Typed Logic for Cyber-Physical Systems. ACM Trans. Embed. Comput. Syst. Gokul Hariharan, Brian Kempa, Tichakorn Wongpiromsarn, Phillip H. Jones, Kristin Y. Rozier
2025	B	`conf`	R2U2 Playground: Visualization of a Real-time, Temporal Logic Runtime Monitor. FMCAD Alexis A. Aurandt, Kristin Yvonne Rozier, Phillip H. Jones
2025	B	`conf`	Scalable MLTL Runtime Monitoring and Satisfiability via Bit-Vector Encoding. FMCAD Christopher Johannsen, Phillip H. Jones, Kristin Yvonne Rozier, Tichakorn Wongpiromsarn
2025	—	`conf`	Towards a Safe, Verified Runtime Monitor for Embedded Systems: R2U2 in Embedded Rust. NFM Alexis A. Aurandt, Phillip H. Jones, Kristin Yvonne Rozier
2024	C	`conf`	Multimodal Model Predictive Runtime Verification for Safety of Autonomous Cyber-Physical Systems. FMICS Alexis A. Aurandt, Phillip H. Jones, Kristin Yvonne Rozier, Tichakorn Wongpiromsarn
2023	C	`conf`	Case Studies in Applying Design Thinking to Course Design in Computer Engineering. FIE Diane T. Rover, Henry Duwe, Phillip H. Jones, Nicholas D. Fila, Mani Mina
2023	C	`conf`	Impossible Made Possible: Encoding Intractable Specifications via Implied Domain Constraints. FMICS Chris Johannsen, Brian Kempa, Phillip H. Jones, Kristin Y. Rozier, Tichakorn Wongpiromsarn
2023	—	`conf`	Maximum Satisfiability of Mission-Time Linear Temporal Logic. FORMATS Gokul Hariharan, Phillip H. Jones, Kristin Yvonne Rozier, Tichakorn Wongpiromsarn
2023	—	`conf`	Model Predictive Runtime Verification for Cyber-Physical Systems with Real-Time Deadlines. FORMATS Pei Zhang, Alexis A. Aurandt, Rohit Dureja, Phillip H. Jones, Kristin Yvonne Rozier
2023	—	`conf`	R2U2 Version 3.0: Re-Imagining a Toolchain for Specification, Resource Estimation, and Optimized Observer Generation for Runtime Verification in Hardware and Software. CAV (3) Chris Johannsen, Phillip H. Jones, Brian Kempa, Kristin Yvonne Rozier, Pei Zhang
2022	C	`conf`	Defining and Supporting a Debugging Mindset in Computer Engineering Courses. FIE Henry Duwe, Diane T. Rover, Phillip H. Jones, Nicholas D. Fila, Mani Mina
2022	J	`jnl`	Integrating runtime verification into an automated UAS traffic management system. Innov. Syst. Softw. Eng. Abigail Hammer, Matthew Cauwels, Benjamin Hertz, Phillip H. Jones, Kristin Y. Rozier
2022	—	`conf`	MLTL Multi-type (MLTLM): A Logic for Reasoning About Signals of Different Types. NSV/FoMLAS@CAV Gokul Hariharan, Brian Kempa, Tichakorn Wongpiromsarn, Phillip H. Jones, Kristin Y. Rozier
2022	—	`conf`	Runtime Verification Triggers Real-Time, Autonomous Fault Recovery on the CySat-I. NFM Alexis A. Aurandt, Phillip H. Jones, Kristin Yvonne Rozier
2021	—	`conf`	An Efficient Hardware Architecture for Sparse Convolution using Linear Feedback Shift Registers. ASAP Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones
2021	J	`jnl`	Benchmarking vision kernels and neural network inference accelerators on embedded platforms. J. Syst. Archit. Murad Qasaimeh, Kristof Denolf, Alireza Khodamoradi, Michaela Blott, Jack Lo, Lisa Halder, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones
2021	C	`conf`	Learning and Professional Development Through Integrated Reflective Activities in Electrical and Computer Engineering Courses. FIE Diane T. Rover, Henry J. Duwe III, Mani Mina, Nicholas D. Fila, Phillip H. Jones, Lindsey S. Sleeth
2020	—	`conf`	Embedding Online Runtime Verification for Fault Disambiguation on Robonaut2. FORMATS Brian Kempa, Pei Zhang, Phillip H. Jones, Joseph Zambreno, Kristin Yvonne Rozier
2020	—	`conf`	Integrating Runtime Verification into an Automated UAS Traffic Management System. ECSA Companion Matthew Cauwels, Abigail Hammer, Benjamin Hertz, Phillip H. Jones, Kristin Y. Rozier
2020	C	`conf`	Introducing Autonomy in an Embedded Systems Course Project. FIE Diane T. Rover, Nicholas D. Fila, Phillip H. Jones, Mani Mina
2020	—	`conf`	ParaHist: FPGA Implementation of Parallel Event-Based Histogram for Optical Flow Calculation. ASAP Mohammad Pivezhandi, Phillip H. Jones, Joseph Zambreno
2019	Misc	`conf`	Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms. FCCM Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones, Kristof Denolf, Jack Lo, Kees A. Vissers
2019	—	`conf`	Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels. ICESS Murad Qasaimeh, Kristof Denolf, Jack Lo, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones
2019	J	`jnl`	Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels. CoRR Murad Qasaimeh, Kristof Denolf, Jack Lo, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones
2018	B	`conf`	A Runtime Configurable Hardware Architecture for Computing Histogram-Based Feature Descriptors. FPL Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones
2018	J	`jnl`	ARMOR: A Recompilation and Instrumentation-Free Monitoring Architecture for Detecting Memory Exploits. IEEE Trans. Computers Alex Grieve, Michael Davies, Phillip H. Jones, Joseph Zambreno
2018	—	`conf`	An FPGA-based Hardware Accelerator for Iris Segmentation. ReConFig Joe Avey, Phillip H. Jones, Joseph Zambreno
2018	—	`conf`	HW/SW Configurable LQG Controller using a Sequential Discrete Kalman Filter. ReConFig Matthew Cauwels, Joseph Zambreno, Phillip H. Jones
2017	—	`conf`	A Modified Sliding Window Architecture for Efficient BRAM Resource Utilization. IPDPS Workshops Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones
2017	—	`conf`	An embedded scalable linear model predictive hardware-based controller using ADMM. ASAP Pei Zhang, Joseph Zambreno, Phillip H. Jones
2017	J	`jnl`	The design and integration of a software configurable and parallelized coprocessor architecture for LQR control. J. Parallel Distributed Comput. Pei Zhang, Aaron Mills, Joseph Zambreno, Phillip H. Jones
2016	J	`jnl`	A Reconfigurable Architecture for the Detection of Strongly Connected Components. ACM Trans. Reconfigurable Technol. Syst. Osama G. Attia, Kevin R. Townsend, Phillip H. Jones, Joseph Zambreno
2016	C	`conf`	Evidence-based planning to broaden the participation of women in electrical and computer engineering. FIE Diane T. Rover, Joseph Zambreno, Mani Mina, Phillip H. Jones, Lora Leigh Chrystal
2016	—	`conf`	Parameterizable FPGA-Based Kalman Filter Coprocessor Using Piecewise Affine Modeling. IPDPS Workshops Aaron Mills, Phillip H. Jones, Joseph Zambreno
2016	J	`jnl`	RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing. IEEE Trans. Parallel Distributed Syst. Chad Nelson, Kevin R. Townsend, Osama G. Attia, Phillip H. Jones, Joseph Zambreno
2015	J	`jnl`	A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns. SIGARCH Comput. Archit. News Xinying Wang, Phillip H. Jones, Joseph Zambreno
2015	J	`jnl`	A Fault-Aware Toolchain Approach for FPGA Fault Tolerance. ACM Trans. Design Autom. Electr. Syst. Adwait Gupte, Sudhanshu Vyas, Phillip H. Jones
2015	J	`jnl`	A Scalable Unsegmented Multiport Memory for FPGA-Based Systems. Int. J. Reconfigurable Comput. Kevin R. Townsend, Osama G. Attia, Phillip H. Jones, Joseph Zambreno
2015	—	`conf`	A project-based embedded systems design course using a reconfigurable SoC platform. MSE Daniel Roggow, Paul Uhing, Phillip H. Jones, Joseph Zambreno
2015	—	`conf`	A software configurable and parallelized coprocessor architecture for LQR control. ReConFig Pei Zhang, Aaron Mills, Joseph Zambreno, Phillip H. Jones
2015	B	`conf`	A software configurable coprocessor-based state-space controller. FPL Aaron Mills, Pei Zhang, Sudhanshu Vyas, Joseph Zambreno, Phillip H. Jones
2015	—	`conf`	Accelerating all-pairs shortest path using a message-passing reconfigurable architecture. ReConFig Osama G. Attia, Alex Grieve, Kevin R. Townsend, Phillip H. Jones, Joseph Zambreno
2015	J	`jnl`	An FPGA Architecture for the Recovery of WPA/WPA2 Keys. J. Circuits Syst. Comput. Tyler Johnson, Daniel Roggow, Phillip H. Jones, Joseph Zambreno
2015	—	`conf`	k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator. EIT Kevin R. Townsend, Song Sun, Tyler Johnson, Osama G. Attia, Phillip H. Jones, Joseph Zambreno
2014	—	`conf`	A Reconfigurable Architecture for QR Decomposition Using a Hybrid Approach. ISVLSI Xinying Wang, Phillip H. Jones, Joseph Zambreno
2014	C	`conf`	A high performance systolic architecture for k-NN classification. MEMOCODE Kevin Townsend, Phillip H. Jones, Joseph Zambreno
2014	J	`jnl`	An FPGA-Based Plant-on-Chip Platform for Cyber-Physical System Analysis. IEEE Embed. Syst. Lett. Sudhanshu Vyas, Chetan Kumar Ng, Joseph Zambreno, Christopher D. Gill, Ron Cytron, Phillip H. Jones
2014	C	`conf`	Cache design for mixed criticality real-time systems. ICCD N. G. Chetan Kumar, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones
2014	—	`conf`	CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search. IPDPS Workshops Osama G. Attia, Tyler Johnson, Kevin Townsend, Phillip H. Jones, Joseph Zambreno
2014	J	`jnl`	Hardware-software architecture for priority queue management in real-time and embedded systems. Int. J. Embed. Syst. N. G. Chetan Kumar, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones
2013	—	`conf`	Design and implementation of an H∞ controller for a quadrotor helicopter. MED Matt Rich, Nicola Elia, Phillip H. Jones
2013	J	`jnl`	Hardware architectural support for control systems and sensor processing. ACM Trans. Embed. Comput. Syst. Sudhanshu Vyas, Adwait Gupte, Christopher D. Gill, Ron K. Cytron, Joseph Zambreno, Phillip H. Jones
2013	Misc	`conf`	Scheduling Challenges in Mixed Critical Real-Time Heterogeneous Computing Platforms. ICCS Chetan Kumar Ng, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones
2012	J	`jnl`	An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. Song Sun, Madhu Monga, Phillip H. Jones, Joseph Zambreno
2012	C	`conf`	Design and evaluation of a delay-based FPGA Physically Unclonable Function. ICCD Aaron Mills, Sudhanshu Vyas, Michael Patterson, Christopher Sabotta, Phillip H. Jones, Joseph Zambreno
2012	Misc	`conf`	Improving System Predictability and Performance via Hardware Accelerated Data Structures. ICCS Chetan Kumar Ng, Sudhanshu Vyas, Jonathan A. Shidal, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones
2012	C	`conf`	Shepard: A fast exact match short read aligner. MEMOCODE Chad Nelson, Kevin Townsend, Bhavani Satyanarayana Rao, Phillip H. Jones, Joseph Zambreno
2011	—	`conf`	Characterizing Non-ideal Impacts of Reconfigurable Hardware Workloads on Ring Oscillator-Based Thermometers. ReConFig Moinuddin Sayed, Phillip H. Jones
2011	C	`conf`	Circumventing a ring oscillator approach to FPGA-based hardware Trojan detection. ICCD Justin Rilling, David Graziano, Jamin Hitchcock, Tim Meyer, Xinying Wang, Phillip H. Jones, Joseph Zambreno
2011	—	`ed.`	Contemporary Computing - 4th International Conference, IC3 2011, Noida, India, August 8-10, 2011. Proceedings IC3 Srinivas Aluru, Sanghamitra Bandyopadhyay, Ümit V. Çatalyürek, Devdatt P. Dubhashi, Phillip H. Jones, Manish Parashar, Bertil Schmidt
2011	—	`conf`	Teaching graphics processing and architecture using a hardware prototyping approach. MSE Michael Steffen, Phillip H. Jones, Joseph Zambreno
2010	A	`conf`	An evaluation of a slice fault aware tool chain. DATE Adwait Gupte, Phillip H. Jones
2010	C	`conf`	CANSCID-CUDA. MEMOCODE Michael Steffen, Veerendra Allada, Phillip H. Jones, Joseph Zambreno
2010	C	`conf`	Team [Ii][Ss][Uu][0-2]{4} design overview: MEMOCODE 2010 design contest. MEMOCODE Sudhanshu Vyas, Pooja Mhapsekar, Aditya Ashok, Moinuddin Sayed, Avinash Srinivasa, Gunjan Pandey, Adam Jackson, Matthew Nelson, Anand Saggi, Harini Sundararaman, Phillip H. Jones
2009	—	`conf`	Hotspot Mitigation Using Dynamic Partial Reconfiguration for Improved Performance. ReConFig Adwait Gupte, Phillip H. Jones
2009	B	`conf`	Towards Hardware Support for Common Sensor Processing Tasks. RTCSA Adwait Gupte, Phillip H. Jones
2007	B	`conf`	Adaptive Thermoregulation for Applications on Reconfigurable Devices. FPL Phillip H. Jones, James Moscola, Young H. Cho, John W. Lockwood
2007	Misc	`conf`	Changing Output Quality for Thermal Management. FCCM Phillip H. Jones, James Moscola, Young H. Cho, John W. Lockwood
2007	Misc	`conf`	Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads. VLSI Design Phillip H. Jones, Young H. Cho, John W. Lockwood
2006	B	`conf`	A Thermal Management and Profiling Method for Reconfigurable Hardware Applications. FPL Phillip H. Jones, John W. Lockwood, Young H. Cho
2006	—	`conf`	An adaptive frequency control method using thermal feedback for reconfigurable hardware applications. FPT Phillip H. Jones, Young H. Cho, John W. Lockwood
2005	J	`jnl`	Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures. Int. J. Parallel Program. Shobana Padmanabhan, Phillip H. Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger D. Chamberlain, Ron Cytron, Jason E. Fritts, John W. Lockwood
2005	—	`conf`	Use of a Soft-Core Processor in a Hardware/Software Codesign Laboratory. MSE Roger D. Chamberlain, John W. Lockwood, Saurabh Gayen, Richard Hough, Phillip H. Jones
2004	—	`conf`	Liquid Architecture. IPDPS Next Generation Software Program - NSFNGS - PI Workshop Phillip H. Jones, Shobana Padmanabhan, Daniel Rymarz, John Maschmeyer, David V. Schuehler, John W. Lockwood, Ron Cytron