Philippos Papaphilippou

26 papers A 1B 5Misc 1Journal 15Unranked 4

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	LUTstructions: Self-loading FPGA-based Reconfigurable Instructions. CoRR Philippos Papaphilippou
2025	Misc	`conf`	Efficient Adaptable Streaming Aggregation Engine. FCCM Philippos Papaphilippou, Wayne Luk, David Gregg
2025	J	`jnl`	Juniper: A 3D plotting framework for effective multi-dimensional scatterplots. SoftwareX Philippos Papaphilippou
2024	J	`jnl`	Efficient Adaptable Streaming Aggregation Engine. CoRR Philippos Papaphilippou, Wayne Luk
2024	J	`jnl`	Efficient Deadlock Avoidance for 2-D Mesh NoCs That Use OQ or VOQ Routers. IEEE Trans. Computers Philippos Papaphilippou, Thiem Van Chu
2024	J	`jnl`	Revisiting 3D Cartesian Scatterplots with a Novel Plotting Framework and a Survey. CoRR Philippos Papaphilippou
2023	J	`jnl`	Efficient deadlock avoidance in 2D mesh NoCs that use OQ or VOQ routers. CoRR Philippos Papaphilippou
2023	—	`conf`	Efficiently Removing Sparsity for High-Throughput Stream Processing. ICFPT Philippos Papaphilippou, Zhiqiang Que, Wayne Luk
2023	J	`jnl`	Experimental Survey of FPGA-Based Monolithic Switches and a Novel Queue Balancer. IEEE Trans. Parallel Distributed Syst. Philippos Papaphilippou, Kentaro Sano, Boma Anantasatya Adhi, Wayne Luk
2022	J	`jnl`	FLiMS: A Fast Lightweight 2-Way Merger for Sorting. IEEE Trans. Computers Philippos Papaphilippou, Wayne Luk, Chris Brooks
2022	—	`conf`	FPGA-Extended General Purpose Computer Architecture. ARC Philippos Papaphilippou, Myrtle Shah
2022	J	`jnl`	FPGA-extended Modified Harvard Architecture. CoRR Philippos Papaphilippou
2022	J	`jnl`	Hipernetch: High-Performance FPGA Network Switch. ACM Trans. Reconfigurable Technol. Syst. Philippos Papaphilippou, Jiuxi Meng, Nadeen Gebara, Wayne Luk
2021	B	`conf`	Demonstrating custom SIMD instruction development for a RISC-V softcore. FPL Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk
2021	—	`conf`	Efficient Queue-Balancing Switch for FPGAs. FPT Philippos Papaphilippou, Kentaro Sano, Boma A. Adhi, Wayne Luk
2021	J	`jnl`	Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions. CoRR Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk
2021	J	`jnl`	FLiMS: a Fast Lightweight 2-way Merge Sorter. CoRR Philippos Papaphilippou, Wayne Luk, Chris Brooks
2021	B	`conf`	Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions. FPL Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk
2020	B	`conf`	An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics. FPL Philippos Papaphilippou, Chris Brooks, Wayne Luk
2020	A	`conf`	High-Performance FPGA Network Switch Architecture. FPGA Philippos Papaphilippou, Jiuxi Meng, Wayne Luk
2019	J	`jnl`	Accelerating Hybrid Monte Carlo simulations of the Hubbard model on the hexagonal lattice. Comput. Phys. Commun. Stefan Krieg, Thomas Luu, Johann Ostmeyer, Philippos Papaphilippou, Carsten Urbach
2019	B	`conf`	Accelerating the Merge Phase of Sort-Merge Join. FPL Philippos Papaphilippou, Holger Pirk, Wayne Luk
2019	J	`jnl`	Pangloss: a novel Markov chain prefetcher. CoRR Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk
2018	B	`conf`	Accelerating Database Systems Using FPGAs: A Survey. FPL Philippos Papaphilippou, Wayne Luk
2018	—	`conf`	FLiMS: Fast Lightweight Merge Sorter. FPT Philippos Papaphilippou, Chris Brooks, Wayne Luk
2018	J	`jnl`	Performance tuning for deep learning on a many-core processor (master thesis). CoRR Philippos Papaphilippou