Philippe Lorenzini

12 papers C 1Journal 5Unranked 6

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	40nm SONOS Embedded Select in Trench Memory. ESSDERC Radouane Habhab, Vincenzo Della Marca, Pascal Masson, Nadia Miridi, Clement Pribat, Simon Jeannot, Thibault Kempf, Marc Mantelli, Philippe Lorenzini, Jean-Marc Voisin, Arnaud Régnier, Stephan Niel, Francesco La Rosa
2022	—	`conf`	A Schmitt trigger to benchmark the performance of a new zero-cost transistor. ICECS 2022 Paul Devoge, Hassen Aziza, Philippe Lorenzini, Pascal Masson, Alexandre Malherbe, Franck Julien, Abderrezak Marzaki, Arnaud Régnier, Stephan Niel
2022	C	`conf`	Digital-to-analog converters to benchmark the matching performance of a new zero-cost transistor. ISCAS Paul Devoge, Hassen Aziza, Philippe Lorenzini, Alexandre Malherbe, Franck Julien, Abderrezak Marzaki, Arnaud Régnier, Stephan Niel
2021	—	`conf`	Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology. DTIS Paul Devoge, Hassen Aziza, Philippe Lorenzini, Franck Julien, Abderrezak Marzaki, Alexandre Malherbe, Marc Mantelli, Thomas Sardin, Sébastien Haendler, Arnaud Régnier, Stephan Niel
2016	J	`jnl`	Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology. J. Low Power Electron. Zhaopeng Wei, Gilles Jacquemod, Philippe Lorenzini, Frédéric Hameau, Emeric de Foucauld, Yves Leduc
2014	J	`jnl`	Low Power 28 nm Fully Depleted Silicon on Insulator 2.45 GHz Phase Locked Loop. J. Low Power Electron. Alexandre Fonseca, Emeric de Foucauld, Philippe Lorenzini, Gilles Jacquemod
2014	—	`conf`	VCO design in SOI technologies. NEWCAS Alexandre Fonseca, Gilles Jacquemod, Yves Leduc, Emeric de Foucauld, Philippe Lorenzini
2013	J	`jnl`	Design space exploration for partially reconfigurable architectures in real-time systems. J. Syst. Archit. François Duhem, Fabrice Muller, Willy Aubry, Bertrand Le Gal, Daniel Négru, Philippe Lorenzini
2013	J	`jnl`	Dynamically reconfigurable entropy coder for multi-standard video adaptation using FaRM. Microprocess. Microsystems François Duhem, Nicolas Marques, Fabrice Muller, Hassan Rabah, Serge Weber, Philippe Lorenzini
2012	J	`jnl`	Reconfiguration time overhead on field programmable gate arrays: reduction and cost model. IET Comput. Digit. Tech. François Duhem, Fabrice Muller, Philippe Lorenzini
2011	—	`conf`	FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA. ARC François Duhem, Fabrice Muller, Philippe Lorenzini
2011	—	`conf`	Methodology for designing partially reconfigurable systems using transaction-level modeling. DASIP François Duhem, Fabrice Muller, Philippe Lorenzini