Philippe Coussy

97 papers A 8B 2C 14Misc 7Journal 29Unranked 36

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Exploring the Contribution of Hardware Shuffling in Securing Low-Cost Symmetric Encryption Devices against Power-Based Side-Channel Attacks: Case Study of an AES-128 on FPGA. ACM Trans. Reconfigurable Technol. Syst. Vianney Lapôtre, Cyrille Chavet, Ghita Harcha, Philippe Coussy
2025	J	`jnl`	Specialized Scalar and SIMD Instructions for Error Correction Codes Decoding on RISC-V Processors. IEEE Access Maël Tourres, Cyrille Chavet, Bertrand Le Gal, Philippe Coussy
2024	J	`jnl`	CREPE: Concurrent Reverse-Modulo-Scheduling and Placement for CGRAs. IEEE Trans. Parallel Distributed Syst. Chilankamol Sunny, Satyajit Das, Kevin J. M. Martin, Philippe Coussy
2024	C	`conf`	SplitMS: Split Modulo-Scheduling for Accelerating Loops Onto CGRAs. DSD Christie Sajitha Sajan, Kevin J. M. Martin, Satyajit Das, Philippe Coussy
2024	—	`conf`	Standalone Nested Loop Acceleration on CGRAs for Signal Processing Applications. DASIP Chilankamol Sunny, Satyajit Das, Kevin J. M. Martin, Philippe Coussy
2023	J	`jnl`	An Efficient and Flexible Stochastic CGRA Mapping Approach. ACM Trans. Embed. Comput. Syst. Satyajit Das, Kevin J. M. Martin, Thomas Peyret, Philippe Coussy
2022	J	`jnl`	Energy Efficient Hardware Loop Based Optimization for CGRAs. J. Signal Process. Syst. Chilankamol Sunny, Satyajit Das, Kevin J. M. Martin, Philippe Coussy
2022	J	`jnl`	Generating Efficient FPGA-based CNN Accelerators from High-Level Descriptions. J. Signal Process. Syst. Nermine Ali, Jean-Marc Philippe, Benoît Tain, Philippe Coussy
2022	—	`ch.`	Protecting Behavioral IPs During Design Time: Key-Based Obfuscation Techniques for HLS in the Cloud. Behavioral Synthesis for Hardware Security Hannah Badier, Jean-Christophe Le Lann, Philippe Coussy, Guy Gogniat
2021	—	`conf`	Exploration and Generation of Efficient FPGA-based Deep Neural Network Accelerators. SiPS Nermine Ali, Jean-Marc Philippe, Benoît Tain, Philippe Coussy
2021	—	`conf`	Extended RISC-V hardware architecture for future digital communication systems. 5GWF Maël Tourres, Cyrille Chavet, Bertrand Le Gal, Jérémie Crenne, Philippe Coussy
2021	J	`jnl`	Floating Point CGRA based Ultra-Low Power DSP Accelerator. J. Signal Process. Syst. Rohit Prasad, Satyajit Das, Kevin J. M. Martin, Philippe Coussy
2021	—	`conf`	Hardware Based Loop Optimization for CGRA Architectures. ARC Chilankamol Sunny, Satyajit Das, Kevin J. M. Martin, Philippe Coussy
2021	A	`conf`	Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis. DATE Hannah Badier, Christian Pilato, Jean-Christophe Le Lann, Philippe Coussy, Guy Gogniat
2020	—	`conf`	Deep Neural Networks Characterization Framework for Efficient Implementation on Embedded Systems. SiPS Nermine Ali, Jean-Marc Philippe, Benoît Tain, Thomas Peyret, Philippe Coussy
2020	Misc	`conf`	Energy Efficient Acceleration Of Floating Point Applications Onto CGRA. ICASSP Satyajit Das, Rohit Prasad, Kevin J. M. Martin, Philippe Coussy
2020	A	`conf`	TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE. DATE Rohit Prasad, Satyajit Das, Kevin J. M. Martin, Giuseppe Tagliavini, Philippe Coussy, Luca Benini, Davide Rossi
2020	C	`conf`	Toward Secured IoT Devices: A Shuffled 8-Bit AES Hardware Implementation. ISCAS Ghita Harcha, Vianney Lapôtre, Cyrille Chavet, Philippe Coussy
2019	J	`jnl`	An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Satyajit Das, Kevin J. M. Martin, Davide Rossi, Philippe Coussy, Luca Benini
2019	J	`jnl`	Clone-Based Encoded Neural Networks to Design Efficient Associative Memories. IEEE Trans. Neural Networks Learn. Syst. Hugues Wouafo, Cyrille Chavet, Philippe Coussy
2019	A	`conf`	Context-memory Aware Mapping for Energy Efficient Acceleration with CGRAs. DATE Satyajit Das, Kevin J. M. Martin, Philippe Coussy
2019	Misc	`conf`	Solving Memory Access Conflicts in LTE-4G Standard. ICASSP Cyrille Chavet, Fabrice Lozachmeur, T. Barguil, A. S. Hussein, Philippe Coussy
2019	A	`conf`	Transient Key-based Obfuscation for HLS in an Untrusted Cloud Environment. DATE Hannah Badier, Jean-Christophe Le Lann, Philippe Coussy, Guy Gogniat
2018	C	`conf`	A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics. ISCAS Satyajit Das, Kevin J. M. Martin, Philippe Coussy, Davide Rossi
2017	C	`conf`	A 142MOPS/mW integrated programmable array accelerator for smart visual processing. ISCAS Satyajit Das, Davide Rossi, Kevin J. M. Martin, Philippe Coussy, Luca Benini
2017	J	`jnl`	A Unified Design Flow to Automatically Generate On-Chip Monitors During High-Level Synthesis of Hardware Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mohamed Ben Hammouda, Philippe Coussy, Loïc Lagadec
2017	—	`conf`	Efficient mapping of CDFG onto coarse-grained reconfigurable array architectures. ASP-DAC Satyajit Das, Kevin J. M. Martin, Philippe Coussy, Davide Rossi, Luca Benini
2017	—	`conf`	Efficient scalable hardware architecture for highly performant encoded neural networks. SiPS Hugues Wouafo, Cyrille Chavet, Philippe Coussy, Robin Danilo
2016	—	`conf`	A Scalable Design Approach to Efficiently Map Applications on CGRAs. ISVLSI Satyajit Das, Thomas Peyret, Kevin J. M. Martin, Gwenolé Corre, Mathieu Thevenin, Philippe Coussy
2016	A	`conf`	A dynamically reconfigurable ECC decoder architecture. DATE Awais Sani, Philippe Coussy, Cyrille Chavet
2016	—	`conf`	Associative Memory based on clustered Neural Networks: Improved model and architecture for Oriented Edge Detection. DASIP Robin Danilo, Hugues Nono Wouafo, Cyrille Chavet, Vincent Gripon, Laura Conde-Canencia, Philippe Coussy
2015	C	`conf`	Algorithm and implementation of an associative memory for oriented edge detection using improved clustered neural networks. ISCAS Robin Danilo, Hooman Jarollahi, Vincent Gripon, Philippe Coussy, Laura Conde-Canencia, Warren J. Gross
2015	J	`jnl`	Fully Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories. ACM J. Emerg. Technol. Comput. Syst. Philippe Coussy, Cyrille Chavet, Hugues Nono Wouafo, Laura Conde-Canencia
2015	C	`conf`	Improving storage of patterns in recurrent neural networks: Clone-based model and architecture. ISCAS Hugues Wouafo, Cyrille Chavet, Philippe Coussy
2015	A	`conf`	In-place memory mapping approach for optimized parallel hardware interleaver architectures. DATE Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy, Awais Sani
2015	J	`jnl`	Large-Scale Spiking Neural Networks using Neuromorphic Hardware Compatible Models. ACM J. Emerg. Technol. Comput. Syst. Jeffrey L. Krichmar, Philippe Coussy, Nikil D. Dutt
2015	—	`conf`	Restricted Clustered Neural Network for Storing Real Data. ACM Great Lakes Symposium on VLSI Robin Danilo, Philippe Coussy, Laura Conde-Canencia, Vincent Gripon, Warren J. Gross
2014	C	`conf`	A HLS-Based Toolflow to Design Next-Generation Heterogeneous Many-Core Platforms with Shared Memory. EUC Paolo Burgio, Andrea Marongiu, Philippe Coussy, Luca Benini
2014	—	`conf`	A design approach to automatically generate on-chip monitors during high-level synthesis of hardware accelerator. ACM Great Lakes Symposium on VLSI Mohamed Ben Hammouda, Philippe Coussy, Loïc Lagadec
2014	C	`conf`	A design approach to automatically synthesize ANSI-C assertions during High-Level Synthesis of hardware accelerators. ISCAS Mohamed Ben Hammouda, Philippe Coussy, Loïc Lagadec
2014	—	`conf`	A memory mapping approach based on network customization to design conflict-free parallel hardware architectures. ACM Great Lakes Symposium on VLSI Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy
2014	—	`conf`	A modeling and code generation framework for critical embedded systems design: From Simulink down to VHDL and Ada/C code. ICECS Mickael Lanoe, Matteo Bordin, Dominique Heller, Philippe Coussy, Cyrille Chavet
2014	A	`conf`	A tightly-coupled hardware controller to improve scalability and programmability of shared-memory heterogeneous clusters. DATE Paolo Burgio, Robin Danilo, Andrea Marongiu, Philippe Coussy, Luca Benini
2014	—	`conf`	An automated design approach to map applications on CGRAs. ACM Great Lakes Symposium on VLSI Thomas Peyret, Gwenolé Corre, Mathieu Thevenin, Kevin J. M. Martin, Philippe Coussy
2014	—	`conf`	Efficient application mapping on CGRAs based on backward simultaneous scheduling/binding and dynamic graph transformations. ASAP Thomas Peyret, Gwenolé Corre, Mathieu Thevenin, Kevin J. M. Martin, Philippe Coussy
2014	Misc	`conf`	Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures. ICASSP Saeed-ur Rehman, Awais Sani, Cyrille Chavet, Philippe Coussy
2013	J	`jnl`	A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm. IEEE Trans. Signal Process. Awais Hussain Sani, Philippe Coussy, Cyrille Chavet
2013	—	`conf`	A conflict-free memory mapping approach to design parallel hardware interleaver architectures with optimized network and controller. SiPS Aroua Briki, Cyrille Chavet, Philippe Coussy
2013	—	`conf`	A memory mapping approach for network and controller optimization in parallel interleaver architectures. ACM Great Lakes Symposium on VLSI Aroua Briki, Cyrille Chavet, Philippe Coussy
2013	—	`conf`	Architecture and programming model support for efficient heterogeneous computing on tigthly-coupled shared-memory clusters. DASIP Paolo Burgio, Andrea Marongiu, Robin Danilo, Philippe Coussy, Luca Benini
2013	B	`conf`	Dynamic branch prediction for high-level synthesis. FPL Vianney Lapotre, Philippe Coussy, Cyrille Chavet, Hugues Wouafo, Robin Danilo
2013	J	`jnl`	Introduction de la prédiction de branchement dans la synthèse de haut niveau. Tech. Sci. Informatiques Vianney Lapotre, Philippe Coussy, Cyrille Chavet
2013	Misc	`conf`	On-chip implementation of memory mapping algorithm to support flexible decoder architecture. ICASSP Saeed-ur Rehman, Awais Sani, Philippe Coussy, Cyrille Chavet
2012	—	`conf`	A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders. SiPS Oscar Sanchez, Michel Jézéquel, Saeed-ur Rehman, Awais Sani, Cyrille Chavet, Philippe Coussy, Christophe Jégo
2012	—	`conf`	A design approach dedicated to network-based and conflict-free parallel interleavers. ACM Great Lakes Symposium on VLSI Aroua Briki, Cyrille Chavet, Philippe Coussy, Eric Martin
2012	J	`jnl`	ESL Design Methodology. J. Electr. Comput. Eng. Deming Chen, Kiyoung Choi, Philippe Coussy, Yuan Xie, Zhiru Zhang
2012	C	`conf`	OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters. DSD Paolo Burgio, Andrea Marongiu, Dominique Heller, Cyrille Chavet, Philippe Coussy, Luca Benini
2011	Misc	`conf`	A methodology based on Transportation problem modeling for designing parallel interleaver architectures. ICASSP Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin
2011	C	`conf`	An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture. ISCAS Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin
2011	—	`conf`	High-Level Synthesis: On the path to ESL design. ASICON Philippe Coussy, Dominique Heller, Cyrille Chavet
2010	—	`conf`	A Design Flow for Critical Embedded Systems. SIES Vincent Lefftz, Jean Bertrand, Hugues Cassé, Christophe Clienti, Philippe Coussy, Laurent Maillet-Contoz, Philippe Mercier, Pierre Moreau, Laurence Pierre, Emmanuel Vaumorin
2010	C	`conf`	A memory mapping approach for parallel interleaver design with multiples read and write accesses. ISCAS Cyrille Chavet, Philippe Coussy
2010	Misc	`conf`	An introduction to the SystemC synthesis subset standard. CODES+ISSS Philippe Coussy, Andrés Takach, Michael McNamara, Mike Meredith
2010	—	`conf`	Bitwidth-aware high-level synthesis for designing low-power DSP applications. ICECS Ghizlane Lhairech-Lebreton, Philippe Coussy, Dominique Heller, Eric Martin
2010	—	`conf`	Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach. ICECS Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin
2010	B	`conf`	Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA. FPL Ghizlane Lhairech-Lebreton, Philippe Coussy, Eric Martin
2010	J	`jnl`	High-Level Synthesis for Designing Multimode Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Cyrille Chavet
2010	J	`jnl`	Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures CoRR Cyrille Chavet, Philippe Coussy, Eric Martin, Pascal Urard
2010	Misc	`conf`	Static Address Generation Easing: a design methodology for parallel interleaver architectures. ICASSP Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2009	J	`jnl`	An Introduction to High-Level Synthesis. IEEE Des. Test Comput. Philippe Coussy, Daniel D. Gajski, Michael Meredith, Andrés Takach
2009	J	`jnl`	Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis. J. Signal Process. Syst. Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin
2009	J	`jnl`	Guest Editors' Introduction: Raising the Abstraction Level of Hardware Design. IEEE Des. Test Comput. Philippe Coussy, Andrés Takach
2008	J	`jnl`	Multiple Word-Length High-Level Synthesis. EURASIP J. Embed. Syst. Philippe Coussy, Ghizlane Lhairech-Lebreton, Dominique Heller
2007	J	`jnl`	A Design Methodology for Space-Time Adapter CoRR Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007	J	`jnl`	A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver CoRR Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007	C	`conf`	A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. ISCAS Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007	A	`conf`	A design flow dedicated to multi-mode architectures for DSP applications. ICCAD Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin
2007	—	`conf`	A design methodology for space-time adapter. ACM Great Lakes Symposium on VLSI Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007	J	`jnl`	Application of a design space exploration tool to enhance interleaver generation CoRR Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007	—	`conf`	Application of a design space exploration tool to enhance interleaver generation. EUSIPCO Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007	—	`conf`	Behavioral description model BDM for design space exploration: A case study of HIS algorithm for MC-CDMA system. EUSIPCO Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin
2007	J	`jnl`	Constrained algorithmic IP design for system-on-chip. Integr. Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
2007	J	`jnl`	Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels CoRR Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007	—	`conf`	Synthesis of Multimode digital signal processing systems. AHS Caaliph Andriamisaina, Emmanuel Casseau, Philippe Coussy
2006	J	`jnl`	A formal method for hardware IP design and integration under I/O and timing constraints. ACM Trans. Embed. Comput. Syst. Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
2006	—	`conf`	Design Space Exploration of DSP Applications Based on Behavioral Description Models. SiPS Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin
2006	J	`jnl`	High-level synthesis under I/O Timing and Memory constraints CoRR Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin
2006	J	`jnl`	Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI CoRR Gwenolé Corre, Philippe Coussy, Pierre Bomel, Eric Senn, Eric Martin
2005	—	`conf`	A more efficient and flexible DSP design flow from Matlab-Simulink [FFT algorithm example]. ICASSP (5) Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin
2005	—	`conf`	High-level synthesis under I/O timing and memory constraints. ISCAS (1) Philippe Coussy, Gwenolé Corre, Eric Senn, Pierre Bomel, Eric Martin
2005	C	`conf`	SystemCmantic: A high level Modelling and Co-Design Framework. FDL Lobna Kriaa, S. Adriano, Emmanuel Vaumorin, R. Nouacer, F. Blanc, S. Pajaniardja, Philippe Coussy, Eric Martin, Dominique Heller, Farhat Thabet, Anne-Marie Fouilliart
2004	—	`conf`	A methodology for IP integration into DSP SoC: a case study of a MAP algorithm for turbo decoder. ICASSP (5) Philippe Coussy, David Gnaedig, Amor Nafkha, Adel Baganne, Emmanuel Boutillon, Eric Martin
2003	C	`conf`	Communication and Timing Constraints Analysis for IP Design and Integration. VLSI-SOC Philippe Coussy, Adel Baganne, Eric Martin
2002	—	`conf`	A design methodology for IP integration. ISCAS (4) Philippe Coussy, Adel Baganne, Eric Martin
2002	—	`conf`	A design methodology for integrating IP into SOC systems. CICC Philippe Coussy, Adel Baganne, Eric Martin
2002	—	`conf`	IP cores integration in DSP System-on-chip designs. EUSIPCO Philippe Coussy, Adel Baganne, Eric Martin
2002	—	`conf`	Virtual component IP re-use in telecommunication systems design: a case study of MPEG-2/JPEG2000 encoder. ICECS Philippe Coussy, Adel Baganne, Eric Martin