Philip Brisk - RankMe

149 papers A* 15A 23B 9C 7Misc 17Journal 43Unranked 32

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	SafarDB: FPGA-Accelerated Distributed Transactions via Replicated Data Types. CoRR Javad Saberlatibari, Prithviraj Yuvaraj, Mohsen Lesani, Philip Brisk, Mohammad Sadoghi
2025	—	`conf`	The Rise and Fall of Automatic Instruction-Set Extensions. ASAP Paolo Ienne, Laura Pozzi, Philip Brisk
2024	J	`jnl`	Error detection using pneumatic logic. CoRR Shane Hoang, Mabel Shehada, Zinal Patel, Minh-Huy Tran, Konstantinos Karydis, Philip Brisk, William H. Grover
2023	A	`conf`	Compiling Functions onto Digital Microfluidics. CGO Tyson Loveless, Philip Brisk
2023	J	`jnl`	FPGA-based Acceleration of Time Series Similarity Prediction: From Cloud to Edge. ACM Trans. Reconfigurable Technol. Syst. Amin Kalantar, Zachary Zimmerman, Philip Brisk
2023	Misc	`conf`	Feature Extraction Accelerator for Streaming Time Series. FCCM Prithviraj Yuvaraj, Amin Akalantar, Eamonn J. Keogh, Philip Brisk
2022	—	`ch.`	Hardware Compilation Using SSA. SSA-based Compiler Design Pedro C. Diniz, Philip Brisk
2022	—	`ch.`	Properties and Flavours. SSA-based Compiler Design Philip Brisk, Fabrice Rastello
2021	J	`jnl`	BioScript: programming safe chemistry on laboratories-on-a-chip. Commun. ACM Jason Ott, Tyson Loveless, Christopher Curtis, Mohsen Lesani, Philip Brisk
2021	J	`jnl`	Dynamic Radial Placement and Routing in Paper Microfluidics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Joshua Potter, William H. Grover, Philip Brisk
2021	Misc	`conf`	FA-LAMP: FPGA-Accelerated Learned Approximate Matrix Profile for Time Series Similarity Prediction. FCCM Amin Kalantar, Zachary Zimmerman, Philip Brisk
2021	—	`conf`	Matrix Profile Index Approximation for Streaming Time Series. IEEE BigData Maryam Shahcheraghi, Trevor Cappon, Samet Oymak, Evangelos E. Papalexakis, Eamonn J. Keogh, Zachary Zimmerman, Philip Brisk
2021	J	`jnl`	Reducing Microfluidic Very Large-Scale Integration (mVLSI) Chip Area by Seam Carving. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Brian Crites, Cody Falzone, Tristan Lopez, Karen Kong, Philip Brisk
2021	—	`conf`	Time- and resource-constrained scheduling for digital microfluidic biochips. ICCPS Tyson Loveless, Jason Ott, Philip Brisk
2020	Misc	`conf`	A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer. VLSID Frédéric Gessler, Philip Brisk, Mirjana Stojilovic
2020	A	`conf`	A performance-optimizing compiler for cyber-physical digital microfluidic biochips. CGO Tyson Loveless, Jason Ott, Philip Brisk
2020	—	`conf`	Acoustic Side Channel Attack Against DNA Synthesis Machines: Poster Abstract. ICCPS Sina Faezi, Sujit Rokka Chhetri, Arnav Vaibhav Malawade, John Charles Chaput, William H. Grover, Philip Brisk, Mohammad Abdullah Al Faruque
2020	J	`jnl`	ChemStor: Using Formal Methods To Guarantee Safe Storage and Disposal of Chemicals. J. Chem. Inf. Model. Jason Ott, Daniel Tan, Tyson Loveless, William H. Grover, Philip Brisk
2020	J	`jnl`	Directed Placement for mVLSI Devices. ACM J. Emerg. Technol. Comput. Syst. Brian Crites, Karen Kong, Philip Brisk
2020	A	`conf`	Tuning floating-point precision using dynamic program information and temporal locality. SC Hugo Brunie, Costin Iancu, Khaled Z. Ibrahim, Philip Brisk, Brandon Cook
2019	—	`conf`	Approximate Adder Tree Synthesis for FPGAs. ReConFig Sina Boroumand, Philip Brisk
2019	J	`jnl`	Hardware-Assisted Cross-Generation Prediction of GPUs Under Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kenneth O'Neal, Philip Brisk, Emily Shriver, Michael Kishinevsky
2019	—	`conf`	Matrix Profile XIV: Scaling Time Series Motif Discovery with GPUs to Break a Quintillion Pairwise Comparisons a Day and Beyond. SoCC Zachary Zimmerman, Kaveh Kamgar, Nader Shakibay Senobari, Brian Crites, Gareth J. Funning, Philip Brisk, Eamonn J. Keogh
2019	A*	`conf`	Matrix Profile XVIII: Time Series Mining in the Face of Fast Moving Streams using a Learned Approximate Matrix Profile. ICDM Zachary Zimmerman, Nader Shakibay Senobari, Gareth J. Funning, Evangelos E. Papalexakis, Samet Oymak, Philip Brisk, Eamonn J. Keogh
2019	A*	`conf`	Oligo-Snoop: A Non-Invasive Side Channel Attack Against DNA Synthesis Machines. NDSS Sina Faezi, Sujit Rokka Chhetri, Arnav Vaibhav Malawade, John Charles Chaput, William H. Grover, Philip Brisk, Mohammad Abdullah Al Faruque
2019	A	`conf`	Specification, Integration, and Benchmarking of Continuous Flow Microfluidic Devices: Invited Paper. ICCAD Radhakrishna Sanka, Brian Crites, Jeffrey McDaniel, Philip Brisk, Douglas Densmore
2019	J	`jnl`	TCAD EIC Message: February 2019. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Philip Brisk, Suman Chakraborty, Claudionor Coelho, Abdoulaye Gamatié, Swaroop Ghosh, Xun Jiao
2018	A	`conf`	A compiler for cyber-physical digital microfluidic biochips. CGO Christopher Curtis, Daniel T. Grissom, Philip Brisk
2018	—	`conf`	Accelerating Simulation of Particle Trajectories in Microfluidic Devices by Constructing a Cloud Database. ISVLSI Junchao Wang, Lingxuan Fu, Liyang Yu, Xiwei Huang, Philip Brisk, William H. Grover
2018	A	`conf`	Approximate quaternary addition with the fast carry chains of FPGAs. DATE Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk
2018	J	`jnl`	BioScript: programming safe chemistry on laboratories-on-a-chip. Proc. ACM Program. Lang. Jason Ott, Tyson Loveless, Christopher Curtis, Mohsen Lesani, Philip Brisk
2018	B	`conf`	Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model. FPL Yehdhih Ould Mohammed Moctar, Mirjana Stojilovic, Philip Brisk
2018	J	`jnl`	Exploiting a novel algorithm and GPUs to break the ten quadrillion pairwise comparisons barrier for time series motifs and joins. Knowl. Inf. Syst. Yan Zhu, Zachary Zimmerman, Nader Shakibay Senobari, Chin-Chia Michael Yeh, Gareth J. Funning, Abdullah Mueen, Philip Brisk, Eamonn J. Keogh
2018	—	`conf`	Exploration of approximate multipliers design space using carry propagation free compressors. ASP-DAC Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk, Siamak Mohammadi
2018	A	`conf`	HLSPredict: cross platform performance prediction for FPGA high-level synthesis. ICCAD Kenneth O'Neal, Mitch Liu, Hans Tang, Amin Kalantar, Kennen DeRenard, Philip Brisk
2018	—	`conf`	ParchMint: A Microfluidics Benchmark Suite. IISWC Brian Crites, Radhakrishna Sanka, Joshua Lippai, Jeffrey McDaniel, Philip Brisk, Douglas Densmore
2018	—	`conf`	Predictive Modeling for CPU, GPU, and FPGA Performance and Power Consumption: A Survey. ISVLSI Kenneth O'Neal, Philip Brisk
2018	J	`jnl`	Resource-Constrained Scheduling for Digital Microfluidic Biochips. ACM J. Emerg. Technol. Comput. Syst. Kenneth O'Neal, Daniel T. Grissom, Philip Brisk
2018	J	`jnl`	Scheduling and Fluid Routing for Flow-Based Microfluidic Laboratories-on-a-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wajid Hassan Minhass, Jeffrey McDaniel, Michael Lander Raagaard, Philip Brisk, Paul Pop, Jan Madsen
2018	J	`jnl`	Stationary-Mixing Field-Programmable Pin-Constrained Digital Microfluidic Biochip. Microelectron. J. Alireza Abdoli, Philip Brisk
2017	Misc	`conf`	An Out-of-Order Load-Store Queue for Spatial Computing. FCCM Lana Josipovic, Philip Brisk, Paolo Ienne
2017	J	`jnl`	An Out-of-Order Load-Store Queue for Spatial Computing. ACM Trans. Embed. Comput. Syst. Lana Josipovic, Philip Brisk, Paolo Ienne
2017	A*	`conf`	Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking. DAC Andrew Becker, Wei Hu, Yu Tai, Philip Brisk, Ryan Kastner, Paolo Ienne
2017	—	`conf`	CAL: Exploring cost, accuracy, and latency in approximate and speculative adder design. DFT Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk, Siamak Mohammadi
2017	—	`conf`	Design Automation for Paper Microfluidics with Passive Flow Substrates. ACM Great Lakes Symposium on VLSI Joshua Potter, William H. Grover, Philip Brisk
2017	J	`jnl`	Diagonal Component Expansion for Flow-Layer Placement of Flow-Based Microfluidic Biochips. ACM Trans. Embed. Comput. Syst. Brian Crites, Karen Kong, Philip Brisk
2017	Misc	`conf`	From C to elastic circuits. ACSSC Lana Josipovic, Philip Brisk, Paolo Ienne
2017	J	`jnl`	GPU Performance Estimation using Software Rasterization and Machine Learning. ACM Trans. Embed. Comput. Syst. Kenneth O'Neal, Philip Brisk, Ahmed Abousamra, Zack Waters, Emily Shriver
2017	A*	`conf`	HALWPE: Hardware-Assisted Light Weight Performance Estimation for GPUs. DAC Kenneth O'Neal, Philip Brisk, Emily Shriver, Michael Kishinevsky
2017	J	`jnl`	PCB Escape Routing and Layer Minimization for Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jeffrey McDaniel, Zachary Zimmerman, Daniel T. Grissom, Philip Brisk
2017	J	`jnl`	Performance Improvements and Congestion Reduction for Routing-Based Synthesis for Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Skyler Windh, Calvin Phung, Daniel T. Grissom, Paul Pop, Philip Brisk
2017	—	`conf`	Reducing Microfluidic Very Large Scale Integration (mVLSI) Chip Area by Seam Carving. ACM Great Lakes Symposium on VLSI Brian Crites, Karen Kong, Philip Brisk
2017	A	`conf`	The case for semi-automated design of microfluidic very large scale integration (mVLSI) chips. DATE Jeffrey McDaniel, William H. Grover, Philip Brisk
2016	B	`ed.`	26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016 FPL Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele
2016	A*	`conf`	Matrix Profile II: Exploiting a Novel Algorithm and GPUs to Break the One Hundred Million Barrier for Time Series Motifs and Joins. ICDM Yan Zhu, Zachary Zimmerman, Nader Shakibay Senobari, Chin-Chia Michael Yeh, Gareth J. Funning, Abdullah Mueen, Philip Brisk, Eamonn J. Keogh
2016	B	`conf`	Preface. FPL Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele
2015	J	`jnl`	An open-source compiler and PCB synthesis tool for digital microfluidic biochips. Integr. Daniel T. Grissom, Christopher Curtis, Skyler Windh, Calvin Phung, Navin Kumar, Zachary Zimmerman, Kenneth O'Neal, Jeffrey McDaniel, Nick Liao, Philip Brisk
2015	J	`jnl`	Automatic Application of Power Analysis Countermeasures. IEEE Trans. Computers Ali Galip Bayrak, Francesco Regazzoni, David Novo, Philip Brisk, François-Xavier Standaert, Paolo Ienne
2015	J	`jnl`	Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yehdhih Ould Mohammed Moctar, Guy G. F. Lemieux, Philip Brisk
2015	J	`jnl`	Flow-Layer Physical Design for Microchips Based on Monolithic Membrane Valves. IEEE Des. Test Jeffrey McDaniel, Brian Crites, Philip Brisk, William H. Grover
2015	J	`jnl`	Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation. ACM Trans. Reconfigurable Technol. Syst. Bailey Miller, Frank Vahid, Tony Givargis, Philip Brisk
2015	Misc	`conf`	Rapid online fault recovery for cyber-physical digital microfluidic biochips. VTS Christopher Jaress, Philip Brisk, Daniel T. Grissom
2014	J	`jnl`	A Low-Cost Field-Programmable Pin-Constrained Digital Microfluidic Biochip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daniel T. Grissom, Jeffrey McDaniel, Philip Brisk
2014	Misc	`conf`	Accelerating the dynamic time warping distance measure using logarithmetic arithmetic. ACSSC Joseph Tarango, Eamonn J. Keogh, Philip Brisk
2014	—	`conf`	Exploring speed and energy tradeoffs in droplet transport for digital microfluidic biochips. ASP-DAC Johnathan Fiske, Daniel T. Grissom, Philip Brisk
2014	J	`jnl`	Fast Online Synthesis of Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daniel T. Grissom, Philip Brisk
2014	J	`jnl`	Interpreting Assays with Control Flow on Digital Microfluidic Biochips. ACM J. Emerg. Technol. Comput. Syst. Daniel T. Grissom, Christopher Curtis, Philip Brisk
2014	C	`conf`	Multi-terminal PCB escape routing for digital microfluidic biochips using negotiated congestion. VLSI-SoC Jeffrey McDaniel, Daniel T. Grissom, Philip Brisk
2014	A*	`conf`	Parallel FPGA Routing based on the Operator Formulation. DAC Yehdhih Ould Mohammed Moctar, Philip Brisk
2014	—	`conf`	Performance and cost analysis of NoC-inspired virtual topologies for digital microfluidic biochips. ISIC Daniel T. Grissom, Jeffrey McDaniel, Philip Brisk
2014	C	`conf`	Simulated annealing-based placement for microfluidic large scale integration (mLSI) chips. VLSI-SoC Jeffrey McDaniel, Brendon Parker, Philip Brisk
2014	J	`jnl`	Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage. ACM Trans. Archit. Code Optim. Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne
2014	J	`jnl`	Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions. IEEE Trans. Very Large Scale Integr. Syst. Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne
2013	A*	`conf`	A field-programmable pin-constrained digital microfluidic biochip. DAC Daniel T. Grissom, Philip Brisk
2013	A	`conf`	A just-in-time customizable processor. ICCAD Liang Chen, Joseph Tarango, Tulika Mitra, Philip Brisk
2013	A	`conf`	An EDA-friendly protection scheme against side-channel attacks. DATE Ali Galip Bayrak, Nikola Velickovic, Francesco Regazzoni, David Novo, Philip Brisk, Paolo Ienne
2013	—	`conf`	Automatic synthesis of microfluidic large scale integration chips from a domain-specific language. BioCAS Jeffrey McDaniel, Christopher Curtis, Philip Brisk
2013	—	`conf`	Design and verification tools for continuous fluid flow-based microfluidic devices. ASP-DAC Jeffrey McDaniel, Auralila Baez, Brian Crites, Aditya Tammewar, Philip Brisk
2013	Misc	`conf`	Instruction set extensions for Dynamic Time Warping. CODES+ISSS Joseph Tarango, Eamonn J. Keogh, Philip Brisk
2013	J	`jnl`	Introduction to the special issue on application-specific processors. ACM Trans. Embed. Comput. Syst. Philip Brisk, Tulika Mitra
2013	—	`ed.`	Reconfigurable Computing: Architectures, Tools and Applications - 9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25-27, 2013. Proceedings ARC Philip Brisk, José Gabriel F. Coutinho, Pedro C. Diniz
2013	J	`jnl`	Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne
2013	B	`conf`	Shared memory heterogeneous computation on PCIe-supported platforms. FPL Sambit Kumar Shukla, Yang Yang, Laxmi N. Bhuyan, Philip Brisk
2012	C	`conf`	A digital microfluidic biochip synthesis framework. VLSI-SoC Daniel T. Grissom, Kenneth O'Neal, Benjamin Preciado, Hiral Patel, Robert Doherty, Nick Liao, Philip Brisk
2012	—	`conf`	A high-performance online assay interpreter for digital microfluidic biochips. ACM Great Lakes Symposium on VLSI Daniel T. Grissom, Philip Brisk
2012	—	`conf`	Counting stream registers: An efficient and effective snoop filter architecture. ICSAMOS Aanjhan Ranganathan, Ali Galip Bayrak, Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne
2012	Misc	`conf`	Fast online synthesis of generally programmable digital microfluidic biochips. CODES+ISSS Daniel T. Grissom, Philip Brisk
2012	C	`conf`	Force-Directed List Scheduling for Digital Microfluidic Biochips. VLSI-SoC Kenneth O'Neal, Daniel T. Grissom, Philip Brisk
2012	A*	`conf`	Path scheduling on digital microfluidic biochips. DAC Daniel T. Grissom, Philip Brisk
2012	A	`conf`	Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. FPGA Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk
2012	B	`conf`	Routing algorithms for FPGAS with sparse intra-cluster routing crossbars. FPL Yehdhih Ould Mohammed Moctar, Guy G. F. Lemieux, Philip Brisk
2012	J	`jnl`	SSI Properties Revisited. ACM Trans. Embed. Comput. Syst. Benoit Boissinot, Philip Brisk, Alain Darte, Fabrice Rastello
2012	A	`conf`	Selective flexibility: Breaking the rigidity of datapath merging. DATE Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne
2011	A*	`conf`	A first step towards automatic application of power analysis countermeasures. DAC Ali Galip Bayrak, Francesco Regazzoni, Philip Brisk, François-Xavier Standaert, Paolo Ienne
2011	—	`conf`	Architecture and design automation for application-specific processors. ASICON Philip Brisk
2011	J	`jnl`	Compressor tree synthesis on commercial high-performance FPGAs. ACM Trans. Reconfigurable Technol. Syst. Hadi Parandeh-Afshar, Arkosnato Neogy, Philip Brisk, Paolo Ienne
2011	Misc	`conf`	Graph-coloring and treescan register allocation using repairing. CASES Quentin Colombet, Benoit Boissinot, Philip Brisk, Sebastian Hack, Fabrice Rastello
2011	A	`conf`	Reducing the pressure on routing resources of FPGAs with generic logic chains. FPGA Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne
2010	—	`conf`	A high-level synthesis flow for custom instruction set extensions for application-specific processors. ASP-DAC Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul
2010	J	`jnl`	An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Philip Brisk, Ajay Kumar Verma, Paolo Ienne
2010	J	`jnl`	Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2010	J	`jnl`	Improving FPGA Performance for Carry-Save Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2010	B	`conf`	Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. FPL Amit Verma, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2010	—	`conf`	Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions. HiPEAC Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne
2009	A	`conf`	3D configuration caching for 2D FPGAs. FPGA Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj
2009	A	`conf`	A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. CHES Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009	—	`conf`	A flexible DSP block to enhance FPGA arithmetic performance. FPT Hadi Parandeh-Afshar, Alessandro Cevrero, Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009	J	`jnl`	An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor. ACM Trans. Reconfigurable Technol. Syst. Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2009	J	`jnl`	An approximation algorithm for scheduling on heterogeneous reconfigurable resources. ACM Trans. Embed. Comput. Syst. Ani Nahapetian, Philip Brisk, Soheil Ghiasi, Majid Sarrafzadeh
2009	—	`conf`	Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications. SiPS Jani Boutellier, Alessandro Cevrero, Philip Brisk, Paolo Ienne
2009	—	`conf`	Arithmetic optimization for custom instruction set synthesis. SASP Ajay Kumar Verma, Yi Zhu, Philip Brisk, Paolo Ienne
2009	C	`conf`	Challenges in Automatic Optimization of Arithmetic Circuits. IEEE Symposium on Computer Arithmetic Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2009	B	`conf`	Exploiting fast carry-chains of FPGAs for designing compressor trees. FPL Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2009	Misc	`conf`	FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. FCCM Arun Paidimarri, Alessandro Cevrero, Philip Brisk, Paolo Ienne
2009	J	`jnl`	Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. ACM Trans. Reconfigurable Technol. Syst. Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009	—	`conf`	Hybrid LZA: a near optimal implementation of the leading zero anticipator. ASP-DAC Amit Verma, Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2009	—	`conf`	Introducing control-flow inclusion to support pipelining in custom instruction set extensions. SASP Marcela Zuluaga, Theo Kluter, Philip Brisk, Nigel P. Topham, Paolo Ienne
2009	A	`conf`	Iterative layering: Optimizing arithmetic circuits by structuring the information flow. ICCAD Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2009	—	`conf`	MPSoC Design Using Application-Specific Architecturally Visible Communication. HiPEAC Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne
2009	A	`conf`	Memory organization and data layout for instruction set extensions with architecturally visible storage. ICCAD Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009	J	`jnl`	Optimistic chordal coloring: a coalescing heuristic for SSA form programs. Des. Autom. Embed. Syst. Philip Brisk, Ajay Kumar Verma, Paolo Ienne
2009	A*	`conf`	Thermal-aware data flow analysis. DAC José Luis Ayala, David Atienza, Philip Brisk
2009	B	`conf`	Using 3D integration technology to realize multi-context FPGAs. FPL Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009	A*	`conf`	Way Stealing: cache-assisted automatic instruction set extensions. DAC Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon
2008	A	`conf`	A novel FPGA logic block for improved arithmetic performance. FPGA Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2008	A	`conf`	Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne
2008	J	`jnl`	Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2008	Misc	`conf`	Design space exploration for field programmable compressor trees. CASES Seyed-Hosein Attarzadeh-Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne
2008	—	`conf`	Efficient synthesis of compressor trees on FPGAs. ASP-DAC Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2008	—	`conf`	Fast, quasi-optimal, and pipelined instruction-set extensions. ASP-DAC Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2008	A	`conf`	Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. DATE Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2008	—	`conf`	Scheduling of dataflow models within the Reconfigurable Video Coding framework. SiPS Jani Boutellier, Veeranjaneyulu Sadhanala, Christophe Lucarz, Philip Brisk, Marco Mattavelli
2008	Misc	`conf`	Speculative DMA for architecturally visible storage in instruction set extensions. CODES+ISSS Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon
2008	A	`conf`	Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. DATE Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2007	Misc	`conf`	An optimistic and conservative register assignment heuristic for chordal graphs. CASES Philip Brisk, Ajay Kumar Verma, Paolo Ienne
2007	—	`conf`	Delay aware, reconfigurable security for embedded systems. BODYNETS Tammara Massey, Philip Brisk, Foad Dabiri, Majid Sarrafzadeh
2007	A*	`conf`	Enhancing FPGA Performance for Arithmetic Circuits. DAC Philip Brisk, Ajay Kumar Verma, Paolo Ienne, Hadi Parandeh-Afshar
2007	C	`conf`	Interference graphs for procedures in static single information form are interval graphs. SCOPES Philip Brisk, Majid Sarrafzadeh
2007	A	`conf`	Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. ICCAD Philip Brisk, Ajay Kumar Verma, Paolo Ienne
2007	A*	`conf`	Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. DAC Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2007	Misc	`conf`	Rethinking custom ISE identification: a new processor-agnostic method. CASES Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2006	A	`conf`	Layout driven data communication optimization for high level synthesis. DATE Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer, Adam Kaplan, Philip Brisk, Majid Sarrafzadeh
2006	J	`jnl`	Optimal register sharing for high-level synthesis of SSA form programs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Philip Brisk, Foad Dabiri, Roozbeh Jafari, Majid Sarrafzadeh
2005	B	`conf`	A dictionary construction technique for code compression systems with echo instructions. LCTES Philip Brisk, Jamie Macbeth, Ani Nahapetian, Majid Sarrafzadeh
2005	Misc	`conf`	Adaptive and fault tolerant medical vest for life-critical medical monitoring. SAC Roozbeh Jafari, Foad Dabiri, Philip Brisk, Majid Sarrafzadeh
2004	A*	`conf`	Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. DAC Philip Brisk, Adam Kaplan, Majid Sarrafzadeh
2004	C	`conf`	Instruction Selection for Compilers that Target Architectures with Echo Instructions. SCOPES Philip Brisk, Ani Nahapetian, Majid Sarrafzadeh
2003	A*	`conf`	Data communication estimation and reduction for reconfigurable systems. DAC Adam Kaplan, Philip Brisk, Ryan Kastner
2002	Misc	`conf`	Instruction generation and regularity extraction for reconfigurable processors. CASES Philip Brisk, Adam Kaplan, Ryan Kastner, Majid Sarrafzadeh