Petr Fiser

63 papers A 1C 43Misc 1Journal 14Unranked 4
YearRankTypeTitle / Venue / Authors
2025 C conf
Controllability-Based Circuit Similarity Estimation.
DDECS
Michal Zácek, Petr Fiser
2024 C conf
A Comparison of Logic Extraction Methods in Hardware-Translated Neural Networks.
DDECS
Jan Schmidt, Petr Fiser, Miroslav Skrbek
2024 C conf
Adaptive Input Normalization for Quantized Neural Networks.
DDECS
Jan Schmidt, Petr Fiser, Miroslav Skrbek
2024 C conf
Design Objectives for Synthesis of Graphene PN Junction Circuits Based on Two-Level Representation.
DSD
Subrata Das, Arighna Deb, Petr Fiser, Debesh Kumar Das
2024 J jnl
On the Influence of the Laser Illumination on the Logic Cells Current Consumption.
CoRR
Dmytro Petryk, Zoya Dyka, Milos Krstic, Jan Belohoubek, Petr Fiser, Frantisek Steiner, Tomás Blecha, Peter Langendörfer, Ievgen Kabin
2024 J jnl
Structural bias in synthesis of sparsely-specified functions.
it Inf. Technol.
Petr Fiser, Jan Schmidt
2023 — conf
On the Influence of the Laser Illumination on the Logic Cells Current Consumption : First measurement results.
ICECS
Dmytro Petryk, Zoya Dyka, Milos Krstic, Jan Belohoubek, Petr Fiser, Frantisek Steiner, Tomás Blecha, Peter Langendörfer, Ievgen Kabin
2023 C conf
Reducing Output Response Aliasing Using Boolean Optimization Techniques.
DDECS
Robert Hülle, Petr Fiser, Jan Schmidt
2023 — conf
Switching Activity Reduction in Graphene PN Junction Circuits using Circuit Re-structuring.
ISDCS
Subrata Das, Arighna Deb, Petr Fiser
2022 C conf
A Design Space Exploration Framework for Memristor-Based Crossbar Architecture.
DDECS
Mario Barbareschi, Alberto Bosio, Ian O'Connor, Petr Fiser, Marcello Traiola
2021 C conf
Emerging Technologies: Challenges and Opportunities for Logic Synthesis.
DDECS
Alberto Bosio, Mayeul Cantan, Cédric Marchand, Ian O'Connor, Petr Fiser, Arnaud Poittevin, Marcello Traiola
2021 Misc conf
Minimization of Switching Activity of Graphene Based Circuits.
VLSID
Subrata Das, Petr Fiser, Soumya Pandit, Debesh Kumar Das
2020 C conf
Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing.
DSD
Jaroslav Borecký, Robert Hülle, Petr Fiser
2020 J jnl
Special issue on DSD 2018.
Microprocess. Microsystems
Martin Novotný, Petr Fiser
2020 C conf
Standard Cell Tuning Enables Data-Independent Static Power Consumption.
DDECS
Jan Belohoubek, Petr Fiser, Jan Schmidt
2019 C conf
CMOS Illumination Discloses Processed Data.
DSD
Jan Belohoubek, Petr Fiser, Jan Schmidt
2019 J jnl
SAT-Based Generation of Optimum Circuits with Polymorphic Behavior Support.
J. Circuits Syst. Comput.
Petr Fiser, Ivo Hálecek, Jan Schmidt, Václav Simek
2019 C conf
Using Voters May Lead to Secret Leakage.
DDECS
Jan Belohoubek, Petr Fiser, Jan Schmidt
2018 — conf
Optimum polymorphic circuits synthesis method.
DTIS
Petr Fiser, Václav Simek
2018 C conf
Synthesis of Finite State Machines on Memristor Crossbars.
DDECS
Umberto Ferrandino, Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Petr Fiser, Alberto Bosio
2018 J jnl
Towards AND/XOR balanced synthesis: Logic circuits rewriting with XOR.
Microelectron. Reliab.
Ivo Hálecek, Petr Fiser, Jan Schmidt
2018 J jnl
ZATPG: SAT-based test patterns generator with zero-aliasing in temporal compaction.
Microprocess. Microsystems
Robert Hülle, Petr Fiser, Jan Schmidt
2017 C conf
Are XORs in logic synthesis really necessary?
DDECS
Ivo Hálecek, Petr Fiser, Jan Schmidt
2017 J jnl
Error masking method based on the short-duration offline test.
Microprocess. Microsystems
Jan Belohoubek, Petr Fiser, Jan Schmidt
2017 C conf
SAT-Based ATPG for Zero-Aliasing Compaction.
DSD
Robert Hülle, Petr Fiser, Jan Schmidt
2017 C conf
SAT-Based Generation of Optimum Function Implementations with XOR Gates.
DSD
Petr Fiser, Ivo Hálecek, Jan Schmidt
2016 C conf
A new method for path criticality calculation.
DDECS
Róbert Tamási, Miroslav Siebert, Elena Gramatová, Petr Fiser
2016 C conf
A new user-friendly ATPG platform for digital circuits.
DDECS
Marek Lipovský, Ján Svarc, Elena Gramatová, Petr Fiser
2016 C conf
A rule-based approach for minimizing power dissipation of digital circuits.
DDECS
Subrata Das, Parthasarathi Dasgupta, Petr Fiser, Sudip Ghosh, Debesh Kumar Das
2016 C conf
Error Correction Method Based on the Short-Duration Offline Test.
DSD
Jan Belohoubek, Petr Fiser, Jan Schmidt
2015 C conf
Novel C-Element Based Error Detection and Correction Method Combining Time and Area Redundancy.
DSD
Jan Belohoubek, Petr Fiser, Jan Schmidt
2014 J jnl
Asynchronous sum-of-products logic minimization and orthogonalization.
Int. J. Circuit Theory Appl.
Igor Lemberski, Petr Fiser, Ruslan Suleimanov
2014 J jnl
Dual-rail asynchronous logic multi-level implementation.
Integr.
Igor Lemberski, Petr Fiser
2014 C conf
On Robustness of EDA Tools.
DSD
Jan Schmidt, Petr Fiser, Jiri Balcarek
2014 J jnl
On don't cares in test compression.
Microprocess. Microsystems
Jirí Balcárek, Petr Fiser, Jan Schmidt
2014 C conf
PBO-Based Test Compression.
DSD
Jiri Balcarek, Petr Fiser, Jan Schmidt
2014 C conf
Sources of bias in EDA tools and its influence.
DDECS
Petr Fiser, Jan Schmidt, Jiri Balcarek
2013 C conf
Simulation and SAT Based ATPG for Compressed Test Generation.
DSD
Jiri Balcarek, Petr Fiser, Jan Schmidt
2013 J jnl
Techniques for SAT-based constrained test pattern generation.
Microprocess. Microsystems
Jiri Balcarek, Petr Fiser, Jan Schmidt
2013 J jnl
The influence of implementation type on dependability parameters.
Microprocess. Microsystems
Jan Schmidt, Petr Fiser, Jiri Balcarek
2012 C conf
Improving the iterative power of resynthesis.
DDECS
Petr Fiser, Jan Schmidt
2012 C conf
The Influence of Implementation Technology on Dependability Parameters.
DSD
Jan Schmidt, Petr Fiser, Jiri Balcarek
2011 C conf
Techniques for SAT-Based Constrained Test Pattern Generation.
DSD
Jiri Balcarek, Petr Fiser, Jan Schmidt
2010 C conf
Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints.
DSD
Igor Lemberski, Petr Fiser
2010 C conf
On logic synthesis of conventionally hard to synthesize circuits using genetic programming.
DDECS
Petr Fiser, Jan Schmidt, Zdenek Vasícek, Lukás Sekanina
2010 C conf
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG.
DSD
Jiri Balcarek, Petr Fiser, Jan Schmidt
2009 C conf
A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms.
DSD
Petr Fiser, David Toman
2009 C conf
Asynchronous two-level logic of reduced cost.
DDECS
Igor Lemberski, Petr Fiser
2009 C conf
The Case for a Balanced Decomposition Process.
DSD
Jan Schmidt, Petr Fiser
2008 C conf
An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA.
DSD
Petr Fiser, Pavel Kubalík, Hana Kubátová
2008 J jnl
Column-matching based mixed-mode test pattern generator design technique for BIST.
Microprocess. Microsystems
Petr Fiser, Hana Kubátová
2008 C conf
Fast Boolean Minimizer for Completely Specified Functions.
DDECS
Petr Fiser, Pemysl Rucký, Irena Vanová
2007 C conf
Pseudo-Random Pattern Generator Design for Column-Matching BIST.
DSD
Petr Fiser
2006 C conf
Fault Tolerant System Design Method Based on Self-Checking Circuits.
IOLTS
Pavel Kubalík, Petr Fiser, Hana Kubátová
2006 C conf
Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications.
DSD
Petr Fiser, Hana Kubátová
2006 C conf
Multiple-Vector Column-Matching BIST Design Method.
DDECS
Petr Fiser, Hana Kubátová
2004 C conf
Boolean Minimizer FC-Min: Coverage Finding Process.
DSD
Petr Fiser, Hana Kubátová
2004 C conf
Survey of the Algorithms in the Column-Matching BIST Method.
IOLTS
Petr Fiser, Hana Kubátová
2003 J jnl
BOOM - A Heuristic Boolean Minimizer.
Comput. Artif. Intell.
Jan Hlavicka, Petr Fiser
2003 C conf
FC-Min: A Fast Multi-Output Boolean Minimizer.
DSD
Petr Fiser, Jan Hlavicka, Hana Kubátová
2002 — conf
Minimization and Partitioning Method Reducing Input Sets.
DELTA
Jan Hlavicka, Petr Fiser
2001 A conf
BOOM - A Heuristic Boolean Minimizer.
ICCAD
Jan Hlavicka, Petr Fiser
2001 C conf
On the Use of Mutations in Boolean Minimization.
DSD
Petr Fiser, Jan Hlavicka