Peter Zipf - RankMe

112 papers A 4B 29C 12Misc 1Journal 23Unranked 42

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Discovering Optimal Constant Matrix Multiplication Circuits With Boolean Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nicolai Fiege, Peter Zipf
2025	J	`jnl`	Fantastic Circuits and Where to Find Them - A Holistic ILP Formulation for Model-Based Hardware Design. ACM Trans. Reconfigurable Technol. Syst. Nicolai Fiege, Peter Zipf
2025	B	`conf`	Improving Boolean Satisfiability-Based Modulo Scheduling. FPL Nicolai Fiege, Peter Zipf
2025	B	`conf`	Multiplexer Optimizations for Virtex FPGAs. FPL Nicolai Fiege, Martin Hardieck, Peter Zipf
2024	J	`jnl`	Bit-Level Optimized Constant Multiplication Using Boolean Satisfiability. IEEE Trans. Circuits Syst. I Regul. Pap. Nicolai Fiege, Martin Kumm, Peter Zipf
2023	J	`jnl`	BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining. ACM Trans. Reconfigurable Technol. Syst. Nicolai Fiege, Peter Zipf
2023	C	`conf`	More AddNet: A deeper insight into DNNs using FPGA-optimized multipliers. ISCAS Martin Hardieck, Tobias Habermann, Fabian Wagner, Michael Mecik, Martin Kumm, Peter Zipf
2022	Misc	`conf`	Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling. FCCM Nicolai Fiege, Patrick Sittel, Peter Zipf
2022	B	`conf`	Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis. FPL Nicolai Fiege, Patrick Sittel, Peter Zipf
2022	J	`jnl`	Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Patrick Sittel, Nicolai Fiege, John Wickerson, Peter Zipf
2022	B	`conf`	Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals. FPL Nicolai Fiege, Patrick Sittel, Peter Zipf
2021	—	`conf`	Towards Highly Automated Machine-Learning-Empowered Monitoring of Motor Test Stands. ACSOS Diego Botache, Florian Bethke, Martin Hardieck, Maarten Bieshaar, Ludwig Brabetz, Mohamed Ayeb, Peter Zipf, Bernhard Sick
2020	J	`jnl`	AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers. IEEE Trans. Very Large Scale Integr. Syst. Julian Faraone, Martin Kumm, Martin Hardieck, Peter Zipf, Xueyuan Liu, David Boland, Philip H. W. Leong
2020	—	`conf`	Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design. ASP-DAC Patrick Sittel, John Wickerson, Martin Kumm, Peter Zipf
2019	J	`jnl`	AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers. CoRR Julian Faraone, Martin Kumm, Martin Hardieck, Peter Zipf, Xueyuan Liu, David Boland, Philip H. W. Leong
2019	—	`conf`	Efficient Error-Tolerant Quantized Neural Network Accelerators. DFT Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees A. Vissers
2019	J	`jnl`	Efficient Error-Tolerant Quantized Neural Network Accelerators. CoRR Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees A. Vissers
2019	—	`conf`	Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling. ReConFig Patrick Sittel, Nicolai Fiege, Martin Kumm, Peter Zipf
2019	A	`conf`	Reconfigurable Convolutional Kernels for Neural Networks on FPGAs. FPGA Martin Hardieck, Martin Kumm, Konrad Möller, Peter Zipf
2019	J	`jnl`	Unrolling Ternary Neural Networks. CoRR Stephen Tridgell, Martin Kumm, Martin Hardieck, David Boland, Duncan J. M. Moss, Peter Zipf, Philip H. W. Leong
2019	J	`jnl`	Unrolling Ternary Neural Networks. ACM Trans. Reconfigurable Technol. Syst. Stephen Tridgell, Martin Kumm, Martin Hardieck, David Boland, Duncan J. M. Moss, Peter Zipf, Philip H. W. Leong
2018	—	`conf`	Constant Matrix Multiplication with Ternary Adders. ICECS Martin Hardieck, Martin Kumm, Patrick Sittel, Peter Zipf
2018	B	`conf`	ILP-Based Modulo Scheduling and Binding for Register Minimization. FPL Patrick Sittel, Martin Kumm, Julian Oppermann, Konrad Möller, Peter Zipf, Andreas Koch
2018	C	`conf`	Karatsuba with Rectangular Multipliers for FPGAs. ARITH Martin Kumm, Oscar Gustafsson, Florent de Dinechin, Johannes Kappauf, Peter Zipf
2018	J	`jnl`	Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Konrad Möller, Martin Kumm, Mario Garrido, Peter Zipf
2018	J	`jnl`	Optimal Single Constant Multiplication Using Ternary Adders. IEEE Trans. Circuits Syst. II Express Briefs Martin Kumm, Oscar Gustafsson, Mario Garrido, Peter Zipf
2018	—	`conf`	ScaLP: A Light-Weighted (MI)LP-Library. MBMV Patrick Sittel, Thomas Schönwälder, Martin Kumm, Peter Zipf
2017	—	`conf`	High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits. MBMV Patrick Sittel, Martin Kumm, Konrad Möller, Martin Hardieck, Peter Zipf
2017	—	`conf`	Model-based hardware design based on compatible sets of isomorphic subgraphs. FPT Patrick Sittel, Konrad Möller, Martin Kumm, Peter Zipf, Bogdan Pasca, Mark Jervis
2017	J	`jnl`	Optimization of Constant Matrix Multiplication with Low Power and High Throughput. IEEE Trans. Computers Martin Kumm, Martin Hardieck, Peter Zipf
2017	J	`jnl`	Reconfigurable Constant Multiplication for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Konrad Möller, Martin Kumm, Marco Kleinlein, Peter Zipf
2017	C	`conf`	Resource Optimal Design of Large Multipliers for FPGAs. ARITH Martin Kumm, Johannes Kappauf, Matei Istoan, Peter Zipf
2016	J	`jnl`	Comment on "High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs". Int. J. Reconfigurable Comput. Martin Kumm, Peter Zipf
2016	B	`conf`	Efficient sum of absolute difference computation on FPGAs. FPL Martin Kumm, Marco Kleinlein, Peter Zipf
2015	C	`conf`	An Efficient Softcore Multiplier Architecture for Xilinx FPGAs. ARITH Martin Kumm, Shahid Abbas, Peter Zipf
2015	—	`conf`	Efficient structural adder pipelining in transposed form FIR filters. DSP Mathias Faust, Martin Kumm, Chip-Hong Chang, Peter Zipf
2015	J	`jnl`	Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits. CoRR Konrad Möller, Martin Kumm, Charles-Frederic Müller, Peter Zipf
2014	B	`conf`	An FPGA-optimized architecture of horn and schunck optical flow algorithm for real-time applications. FPL Michael Kunz, Alexander Ostrowski, Peter Zipf
2014	—	`conf`	Dynamically Reconfigurable Constant Multiplication on FPGAs. MBMV Konrad Möller, Martin Kumm, Björn Barschtipan, Peter Zipf
2014	—	`conf`	Efficient High Speed Compression Trees on Xilinx FPGAs. MBMV Martin Kumm, Peter Zipf
2014	B	`conf`	Pipelined compressor tree optimization using integer linear programming. FPL Martin Kumm, Peter Zipf
2014	B	`conf`	Pipelined reconfigurable multiplication with constants on FPGAs. FPL Konrad Möller, Martin Kumm, Marco Kleinlein, Peter Zipf
2013	—	`conf`	Dynamically reconfigurable FIR filter architectures with fast reconfiguration. ReCoSoC Martin Kumm, Konrad Möller, Peter Zipf
2013	J	`jnl`	FIR filter optimization for video processing on FPGAs. EURASIP J. Adv. Signal Process. Martin Kumm, Diana Fanghänel, Konrad Möller, Peter Zipf, Uwe Meyer-Baese
2013	B	`conf`	Multiple constant multiplication with ternary adders. FPL Martin Kumm, Martin Hardieck, Jens Willkomm, Peter Zipf, Uwe Meyer-Baese
2013	C	`conf`	Partial LUT size analysis in distributed arithmetic FIR Filters on FPGAs. ISCAS Martin Kumm, Konrad Möller, Peter Zipf
2013	C	`conf`	Reconfigurable FIR filter using distributed arithmetic on FPGAs. ISCAS Martin Kumm, Konrad Möller, Peter Zipf
2012	B	`conf`	Area estimation of look-up table based fixed-point computations on the example of a real-time high dynamic range imaging system. FPL Michael Kunz, Martin Kumm, Martin Heide, Peter Zipf
2012	—	`conf`	Hybrid multiple constant multiplication for FPGAs. ICECS Martin Kumm, Peter Zipf
2012	C	`conf`	Pipelined adder graph optimization for high speed multiple constant multiplication. ISCAS Martin Kumm, Peter Zipf, Mathias Faust, Chip-Hong Chang
2012	B	`conf`	Reduced complexity single and multiple constant multiplication in floating point precision. FPL Martin Kumm, Katharina Liebisch, Peter Zipf
2011	—	`conf`	High speed low complexity FPGA-based FIR filters using pipelined adder graphs. FPT Martin Kumm, Peter Zipf
2010	J	`jnl`	An FPGA-Based Linear All-Digital Phase-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. Martin Kumm, Harald Klingbeil, Peter Zipf
2010	—	`ch.`	Dynamically Reconfigurable Systems for Wireless Sensor Networks. Dynamically Reconfigurable Systems Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2009	J	`jnl`	A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips. Int. J. Reconfigurable Comput. Peter Zipf, Gilles Sassatelli, Nurten Utlu, Nicolas Saint-Jean, Pascal Benoit, Manfred Glesner
2009	B	`conf`	An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs. FPL Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2009	B	`conf`	Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes. FPL Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2009	A	`conf`	Generation of Synthetic Floating-Point benchmark circuits. IPDPS Thomas C. P. Chau, S. Man Ho Ho, Philip Heng Wai Leong, Peter Zipf, Manfred Glesner
2009	J	`jnl`	On the design of reconfigurable multipliers for integer and Galois field multiplication. Microprocess. Microsystems Heiko Hinkelmann, Peter Zipf, Jia Li, Guifang Liu, Manfred Glesner
2009	J	`jnl`	Selected Papers from ReCoSoC 2008. Int. J. Reconfigurable Comput. Michael Hübner, Juan Manuel Moreno, Gilles Sassatelli, Peter Zipf
2009	B	`conf`	Towards a unique FPGA-based identification circuit using process variations. FPL Haile Yu, Philip Heng Wai Leong, Heiko Hinkelmann, Leandro Möller, Manfred Glesner, Peter Zipf
2008	—	`conf`	A scalable reconfiguration mechanism for fast dynamic reconfiguration. FPT Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2008	—	`conf`	An area-efficient FPGA realisation of a codebook-based image compression method. FPT Peter Zipf, Heiko Hinkelmann, Hui Shao, Radu Dogaru, Manfred Glesner
2008	B	`conf`	Application-specific reconfigurable processors. FPL Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Götz Kappen, Tobias G. Noll
2008	J	`jnl`	Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays. IEEE Trans. Very Large Scale Integr. Syst. Peter Zipf
2008	C	`conf`	Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II. IEEE International Workshop on Rapid System Prototyping Christopher Spies, Peter Zipf, Manfred Glesner, Harald Klingbeil
2008	B	`conf`	Coarse-grained reconfiguration. FPL Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2007	—	`conf`	A Customizable LEON2-Based VLIW Processor. ReCoSoC Peter Zipf, Heiko Hinkelmann, Felix Missel, Manfred Glesner
2007	—	`conf`	A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks. FPT Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2007	B	`conf`	A Power Estimation Model for an FPGA-based Softcore Processor. FPL Peter Zipf, Heiko Hinkelmann, Lei Deng, Manfred Glesner, Holger Blume, Tobias G. Noll
2007	J	`jnl`	Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme). it Inf. Technol. Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Thilo Pionteck
2007	—	`conf`	Ein Beitrag zur automatischen Erzeugung dynamisch rekonfigurierbarer Hardwarestrukturen. MBMV Peter Zipf, Yang Qiao, Manfred Glesner
2007	—	`conf`	On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication. ReCoSoC Heiko Hinkelmann, Tudor Murgan, Guifang Liu, Peter Zipf, Manfred Glesner
2006	—	`conf`	A Concept for a Profile-based Dynamic Reconfiguration Mechanism. ReCoSoC Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2006	—	`conf`	A metric for the energy-efficiency of dynamically reconfigurable systems. ARCS Workshops Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2006	A	`conf`	A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits. DATE Oliver Soffke, Peter Zipf, Tudor Murgan, Manfred Glesner
2006	—	`conf`	Design Concepts for a Dynamically ReconfigurableWireless Sensor Node. AHS Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2006	—	`conf`	Eine Scheduling Heuristik zur Minimierung der Verlustleistung. MBMV Peter Zipf, Volker Hampel, Manfred Glesner, Thilo Pionteck
2006	—	`conf`	Implementation of Realtime and Highspeed Phase Detector on FPGA. ARC Andre Guntoro, Peter Zipf, Oliver Soffke, Harald Klingbeil, Martin Kumm, Manfred Glesner
2006	B	`conf`	Multitasking Support for Dynamically Reconfig Urable Systems. FPL Heiko Hinkelmann, Andreas Gunberg, Peter Zipf, Leandro Soares Indrusiak, Manfred Glesner
2006	—	`conf`	Towards an Automated Design of Application-specific Reconfigurable Logic. Dynamically Reconfigurable Architectures Peter Zipf, Manfred Glesner
2005	B	`conf`	A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata. FPL Peter Zipf, Oliver Soffke, Andre Schumacher, Clemens Schlachta, Radu Dogaru, Manfred Glesner
2005	—	`conf`	Abstrakte Modellierung der Eigenschaften von nanoelektronischen CNT-Elementen in SystemC. GI Jahrestagung (1) Peter Zipf, Oliver Soffke, Michael Velten, Manfred Glesner
2005	—	`conf`	Analysis and Architectural Study of a Hybrid ASIC/Configurable State Machine Model. ReCoSoC Peter Zipf, Claude Stötzler, Manfred Glesner
2005	—	`conf`	CONAN - A Design Exploration Framework for Reliable Nano-Electronics. ASAP Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici, Adrian M. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, Antonio Rubio
2005	—	`conf`	Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks. ReCoSoC Tudor Murgan, Abdulfattah Mohammad Obeid, Andre Guntoro, Peter Zipf, Manfred Glesner, Ulrich Heinkel
2005	—	`conf`	Eine weiterentwickelte quasi-statische adiabatische Logikfamilie. GI Jahrestagung (1) Clemens Schlachta, Oliver Soffke, Peter Zipf, Manfred Glesner
2005	—	`conf`	Functional modeling techniques for a wireless LAN OFDM transceiver. ISCAS (4) A. Petrov, Tudor Murgan, Peter Zipf, Manfred Glesner
2005	B	`conf`	Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata. FPL Peter Zipf, Oliver Soffke, Andre Schumacher, Radu Dogaru, Manfred Glesner
2005	—	`conf`	Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques. SAMOS Manfred Glesner, Heiko Hinkelmann, Thomas Hollstein, Leandro Soares Indrusiak, Tudor Murgan, Abdulfattah Mohammad Obeid, Mihail Petrov, Thilo Pionteck, Peter Zipf
2004	—	`conf`	A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture. ISVLSI Peter Zipf, Claude Stötzler, Manfred Glesner
2004	—	`conf`	A switch architecture and signal synchronization for GALS system-on-chips. SBCCI Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner
2004	—	`conf`	Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing. Conf. Computing Frontiers Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel, Jörg Pleickhardt, Bernd Bleisteiner
2004	—	`conf`	An Asynchronous Switch Implmentation for Systems-on-a-Chip. MBMV Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Thomas Hollstein, Manfred Glesner
2004	—	`conf`	Dynamic power optimization of the trace-back process for the Viterbi algorithm. ISCAS (2) Mihail Petrov, Tudor Murgan, Abdulfattah Mohammad Obeid, Cristian Chitu, Peter Zipf, Jörg Brakensiek, Manfred Glesner
2004	—	`conf`	Flexible Overhead Processing Architectures for G.709 Optical Transport Networks. MBMV Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel
2004	B	`conf`	IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter. FPL Ralf Ludewig, Oliver Soffke, Peter Zipf, Manfred Glesner, Kong-Pang Pun, Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong
2004	—	`conf`	Reconfigurable platforms for ubiquitous computing. Conf. Computing Frontiers Manfred Glesner, Thomas Hollstein, Leandro Soares Indrusiak, Peter Zipf, Thilo Pionteck, Mihail Petrov, Heiko Zimmer, Tudor Murgan
2004	B	`conf`	The XPP Architecture and Its Co-simulation Within the Simulink Environment. FPL Mihail Petrov, Tudor Murgan, Frank May, Martin Vorbach, Peter Zipf, Manfred Glesner
2003	A	`conf`	A granularity-based classification model for systems-on-a-chip. FPGA Stephan Bingemer, Peter Zipf, Manfred Glesner
2003	C	`conf`	A hierarchical generic approach for on-chip communication, testing and debugging of SoCs. VLSI-SOC Thomas Hollstein, Ralf Ludewig, Christoph Mager, Peter Zipf, Manfred Glesner
2003	C	`conf`	An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders. VLSI-SOC Mihail Petrov, Abdulfattah Mohammad Obeid, Tudor Murgan, Peter Zipf, Jörg Brakensiek, Bernard Ölkrug, Manfred Glesner
2003	C	`conf`	An Integrated Model Bridging the Gap between Technology and Economy. VLSI-SOC Stephan Bingemer, Peter Zipf, Manfred Glesner
2003	—	`conf`	Arbitrary function approximation in HDLs with application to the N-body problem. FPT Chun Hok Ho, Kuen Hung Tsoi, Jackson H. C. Yeung, Yuet Ming Lam, Kin-Hong Lee, Philip Heng Wai Leong, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner
2003	B	`conf`	Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. FPL Tudor Murgan, Mihail Petrov, Alberto García Ortiz, Ralf Ludewig, Peter Zipf, Thomas Hollstein, Manfred Glesner, Bernard Ölkrug, Jörg Brakensiek
2003	C	`ed.`	IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003 VLSI-SoC Manfred Glesner, Ricardo Augusto da Luz Reis, Hans Eveking, Vincent John Mooney III, Leandro Soares Indrusiak, Peter Zipf
2002	B	`conf`	A Framework for Teaching (Re)Configurable Architectures in Student Projects. FPL Thilo Pionteck, Peter Zipf, Lukusa D. Kabulepa, Manfred Glesner
2002	B	`ed.`	Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings FPL Manfred Glesner, Peter Zipf, Michel Renovell
2002	B	`conf`	Fly - A Modifiable Hardware Compiler. FPL Chun Hok Ho, Philip Heng Wai Leong, Kuen Hung Tsoi, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner
2002	B	`conf`	Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension. FPL Peter Zipf, Manfred Glesner, Christine Bauer, Hans Wojtkowiak
2000	—	`conf`	Integration und Fehlertoleranz im Codesign. MBMV Christine Bauer, Peter Zipf, Hans Wojtkowiak
2000	B	`conf`	System Design with Genetic Algorithms. FPL Christine Bauer, Peter Zipf, Hans Wojtkowiak