Peter Y. K. Cheung

290 papers A* 1A 26B 63C 11Misc 38Journal 74Unranked 76

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Verification and Fault Injection Platform Based on MTB Stimulus Generation Method for L2 Deep Market Quote Decoder. IEEE Access Le Yu, Zhiheng Liang, Yaqi Li, Shiwei Zhang, Yiren Zhao, Peter Y. K. Cheung
2023	J	`jnl`	Enabling Binary Neural Network Training on the Edge. ACM Trans. Embed. Comput. Syst. Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Jia Jie Lim, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides
2023	J	`jnl`	Logic Shrinkage: Learned Connectivity Sparsification for LUT-Based Neural Networks. ACM Trans. Reconfigurable Technol. Syst. Erwei Wang, Marie Auffret, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah, James J. Davis
2022	A	`conf`	Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. FPGA Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah
2021	—	`conf`	Accelerating Recurrent Neural Networks for Gravitational Wave Experiments. ASAP Zhiqiang Que, Erwei Wang, Umar Marikar, Eric A. Moreno, Jennifer Ngadiuba, Hamza Javed, Bartlomiej Borzyszkowski, Thea Aarrestad, Vladimir Loncar, Sioni Summers, Maurizio Pierini, Peter Y. K. Cheung, Wayne Luk
2021	J	`jnl`	Accelerating Recurrent Neural Networks for Gravitational Wave Experiments. CoRR Zhiqiang Que, Erwei Wang, Umar Marikar, Eric A. Moreno, Jennifer Ngadiuba, Hamza Javed, Bartlomiej Borzyszkowski, Thea Aarrestad, Vladimir Loncar, Sioni Summers, Maurizio Pierini, Peter Y. K. Cheung, Wayne Luk
2021	—	`conf`	Enabling Binary Neural Network Training on the Edge. EMDL@MobiSys Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Jia Jie Lim, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides
2021	J	`jnl`	Enabling Binary Neural Network Training on the Edge. CoRR Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides
2021	J	`jnl`	Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. CoRR Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah
2021	J	`jnl`	Post-lockdown abatement of COVID-19 by fast periodic switching. PLoS Comput. Biol. Michelangelo Bin, Peter Y. K. Cheung, Emanuele Crisostomi, Pietro Ferraro, Hugo Lhachemi, Roderick Murray-Smith, Connor W. Myant, Thomas Parisini, Robert Shorten, Sebastian Stein, Lewi Stone
2020	J	`jnl`	LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. IEEE Trans. Computers Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
2020	J	`jnl`	On Fast Multi-Shot Epidemic Interventions for Post Lock-Down Mitigation: Implications for Simple Covid-19 Models. CoRR Michelangelo Bin, Peter Y. K. Cheung, Emanuele Crisostomi, Pietro Ferraro, Connor W. Myant, Thomas Parisini, Robert Shorten
2019	B	`conf`	Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision Regimes. FPL Qiang Li, Erwei Wang, Shane T. Fleming, David B. Thomas, Peter Y. K. Cheung
2019	—	`conf`	Automatic Generation of Multi-Precision Multi-Arithmetic CNN Accelerators for FPGAs. FPT Yiren Zhao, Xitong Gao, Xuan Guo, Junyi Liu, Erwei Wang, Robert Mullins, Peter Y. K. Cheung, George A. Constantinides, Cheng-Zhong Xu
2019	J	`jnl`	Automatic Generation of Multi-precision Multi-arithmetic CNN Accelerators for FPGAs. CoRR Yiren Zhao, Xitong Gao, Xuan Guo, Junyi Liu, Erwei Wang, Robert Mullins, Peter Y. K. Cheung, George A. Constantinides, Cheng-Zhong Xu
2019	J	`jnl`	Context-based image acquisition from memory in digital systems. J. Real Time Image Process. Jianxiong Liu, Christos Bouganis, Peter Y. K. Cheung
2019	J	`jnl`	Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. CoRR Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides
2019	J	`jnl`	Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. ACM Comput. Surv. Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides
2019	J	`jnl`	LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. CoRR Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
2019	Misc	`conf`	LUTNet: Rethinking Inference in FPGA Soft Logic. FCCM Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
2019	J	`jnl`	LUTNet: Rethinking Inference in FPGA Soft Logic. CoRR Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
2018	Misc	`conf`	A PYNQ-Based Framework for Rapid CNN Prototyping. FCCM Erwei Wang, James J. Davis, Peter Y. K. Cheung
2018	—	`conf`	Accelerating Top-k ListNet Training for Ranking Using FPGA. FPT Qiang Li, Shane T. Fleming, David B. Thomas, Peter Y. K. Cheung
2018	—	`conf`	Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic. ARC Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung
2018	J	`jnl`	Accuracy to Throughput Trade-offs for Reduced Precision Neural Networks on Reconfigurable Logic. CoRR Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung
2018	J	`jnl`	CypherDB: A Novel Architecture for Outsourcing Secure Database Processing. IEEE Trans. Cloud Comput. Bony H. K. Chen, Paul Y. S. Cheung, Peter Y. K. Cheung, Yu-Kwong Kwok
2018	—	`conf`	Hardware Compilation of Deep Neural Networks: An Overview. ASAP Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2018	J	`jnl`	KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. ACM Trans. Reconfigurable Technol. Syst. James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
2018	—	`conf`	KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications. IWOCL James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
2018	—	`conf`	Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic for ImageNet Classification. ARC Jiang Su, Julian Faraone, Junyi Liu, Yiren Zhao, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung
2017	J	`jnl`	KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications. IEEE Des. Test James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
2017	B	`conf`	STRIPE: Signal selection for runtime power estimation. FPL James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
2016	Misc	`conf`	Increasing Network Size and Training Throughput of FPGA Restricted Boltzmann Machines Using Dropout. FCCM Jiang Su, David B. Thomas, Peter Y. K. Cheung
2016	Misc	`conf`	KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. FCCM Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
2016	A	`conf`	Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). FPGA James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
2016	J	`jnl`	Neural Network Based Reinforcement Learning Acceleration on FPGA Platforms. SIGARCH Comput. Archit. News Jiang Su, Jianxiong Liu, David B. Thomas, Peter Y. K. Cheung
2016	—	`conf`	Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators. ARC James J. Davis, Peter Y. K. Cheung
2015	—	`conf`	An efficient architecture for zero overhead data en-/decryption using reconfigurable cryptographic engine. FPT Bony H. K. Chen, Paul Y. S. Cheung, Peter Y. K. Cheung, Yu-Kwong Kwok
2015	—	`conf`	G-DMA: improving memory access performance for hardware accelerated sparse graph computation. ReConFig Andrew Bean, Nachiket Kapre, Peter Y. K. Cheung
2015	J	`jnl`	Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems. ACM Trans. Reconfigurable Technol. Syst. Thomas C. P. Chau, Xinyu Niu, Alison Eele, Jan M. Maciejowski, Peter Y. K. Cheung, Wayne Luk
2015	B	`conf`	Preface. FPL Peter Y. K. Cheung, Wayne Luk, Cristina Silvano
2014	B	`conf`	Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration. FPL James J. Davis, Peter Y. K. Cheung
2014	J	`jnl`	Classification on variation maps: a new placement strategy to alleviate process variation on FPGA. IEICE Electron. Express Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2014	A	`conf`	Dynamic voltage & frequency scaling with online slack measurement. FPGA Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung
2014	A	`conf`	Image progressive acquisition for hardware systems. DATE Jianxiong Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung
2014	—	`conf`	Kernel-based Adaptive Image Sampling. VISAPP (1) Jianxiong Liu, Christos Bouganis, Peter Y. K. Cheung
2014	J	`jnl`	Mitigation of process variation effect in FPGAs with partial rerouting method. IEICE Electron. Express Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2014	Misc	`conf`	Reducing Overheads for Fault-Tolerant Datapaths with Dynamic Partial Reconfiguration. FCCM James J. Davis, Peter Y. K. Cheung
2014	Misc	`conf`	SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications. FCCM Thomas C. P. Chau, Maciej Kurek, James Stanley Targett, Jake Humphrey, Georgios Skouroupathis, Alison Eele, Jan M. Maciejowski, Benjamin Cope, Kathryn Cobden, Philip Heng Wai Leong, Peter Y. K. Cheung, Wayne Luk
2014	Misc	`conf`	Timing Fault Detection in FPGA-Based Circuits. FCCM Edward A. Stott, Joshua M. Levine, Peter Y. K. Cheung, Nachiket Kapre
2013	B	`conf`	A variation-adaptive retiming method exploiting reconfigurability. FPL Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2013	J	`jnl`	Accelerating sequential Monte Carlo method for real-time air traffic management. SIGARCH Comput. Archit. News Thomas C. P. Chau, James Stanley Targett, Marlon Wijeyasinghe, Wayne Luk, Peter Y. K. Cheung, Benjamin Cope, Alison Eele, Jan M. Maciejowski
2013	—	`conf`	Acceleration of real-time Proximity Query for dynamic active constraints. FPT Thomas C. P. Chau, Ka-Wai Kwok, Gary C. T. Chow, Kuen Hung Tsoi, Kit-Hang Lee, Zion Tse, Peter Y. K. Cheung, Wayne Luk
2013	—	`conf`	Datapath fault tolerance for parallel accelerators. FPT James J. Davis, Peter Y. K. Cheung
2013	—	`conf`	Domain-specific progressive sampling of face images. GlobalSIP Jianxiong Liu, Christos Bouganis, Peter Y. K. Cheung
2013	—	`conf`	Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting. FPT Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2013	—	`conf`	Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications. ARC Thomas C. P. Chau, Xinyu Niu, Alison Eele, Wayne Luk, Peter Y. K. Cheung, Jan M. Maciejowski
2013	J	`jnl`	High-level power and performance estimation of FPGA-based soft processors and its application to design space exploration. J. Syst. Archit. Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung
2013	B	`conf`	SMI: Slack Measurement Insertion for online timing monitoring in FPGAs. FPL Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung
2013	J	`jnl`	Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability. IEEE Trans. Very Large Scale Integr. Syst. Justin S. J. Wong, Peter Y. K. Cheung
2013	J	`jnl`	Variation and Reliability in FPGAs. IEEE Des. Test Edward A. Stott, Zhenyu Guan, Joshua M. Levine, Justin S. J. Wong, Peter Y. K. Cheung
2012	B	`conf`	A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. FPL Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2012	B	`conf`	Adaptive Sequential Monte Carlo approach for real-time applications. FPL Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung, Alison Eele, Jan M. Maciejowski
2012	B	`conf`	Early performance estimation of image compression methods on soft processors. FPL Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung
2012	Misc	`conf`	Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling. FCCM Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung
2012	J	`jnl`	Roberts: reconfigurable platform for benchmarking real-time systems. SIGARCH Comput. Archit. News Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung
2011	J	`jnl`	A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors. Trans. High Perform. Embed. Archit. Compil. Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes
2011	J	`jnl`	Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network. IEEE Trans. Ind. Electron. Terrence S. T. Mak, Peter Y. K. Cheung, Kai-Pui Lam, Wayne Luk
2011	J	`jnl`	Blur identification with assumption validation for sensor-based video reconstruction and its implementation on field programmable gate array. IET Comput. Digit. Tech. Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung
2011	J	`jnl`	Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization. Comput. J. Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2011	A	`conf`	Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). FPGA Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung
2011	A	`conf`	Improved delay measurement method in FPGA based on transition probability. FPGA Justin S. J. Wong, Peter Y. K. Cheung
2011	B	`conf`	Improving FPGA Reliability with Wear-Levelling. FPL Edward A. Stott, Peter Y. K. Cheung
2011	J	`jnl`	Introduction to special section FPGA 2009. ACM Trans. Reconfigurable Technol. Syst. Peter Y. K. Cheung
2011	—	`conf`	Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates. FPT Sumanta Chaudhuri, Justin S. J. Wong, Peter Y. K. Cheung
2010	—	`conf`	A Salient Region Detector for GPU Using a Cellular Automata Architecture. ICONIP (2) David Huw Jones, Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung
2010	J	`jnl`	An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays. ACM Trans. Reconfigurable Technol. Syst. Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2010	J	`jnl`	Benchmarking and evaluating reconfigurable architectures targeting the mobile domain. ACM Trans. Design Autom. Electr. Syst. Peter Jamieson, Tobias Becker, Peter Y. K. Cheung, Wayne Luk, Tero Rissa, Teemu Pitkänen
2010	B	`conf`	Degradation Analysis and Mitigation in FPGAs. FPL Edward A. Stott, Justin S. J. Wong, Peter Y. K. Cheung
2010	A	`conf`	Degradation in FPGAs: measurement and modelling. FPGA Edward A. Stott, Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung
2010	J	`jnl`	Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods. ACM Trans. Reconfigurable Technol. Syst. Asma Kahoul, Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2010	Misc	`conf`	Energy-Aware Optimisation for Run-Time Reconfiguration. FCCM Tobias Becker, Wayne Luk, Peter Y. K. Cheung
2010	J	`jnl`	Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs. IEEE Trans. Very Large Scale Integr. Syst. Christos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung
2010	A	`conf`	Exploration of hardware sharing for image encoders. DATE Sebastián López, Roberto Sarmiento, Philip G. Potter, Wayne Luk, Peter Y. K. Cheung
2010	J	`jnl`	FPGA Architecture Optimization Using Geometric Programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2010	J	`jnl`	Fault tolerance and reliability in field-programmable gate arrays. IET Comput. Digit. Tech. Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung
2010	B	`conf`	GPU Versus FPGA for High Productivity Computing. FPL David Huw Jones, Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung
2010	J	`jnl`	Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study. IEEE Trans. Computers Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes
2010	J	`jnl`	Power Characterisation for Fine-Grain Reconfigurable Fabrics. Int. J. Reconfigurable Comput. Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa
2010	A	`ed.`	Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010 FPGA Peter Y. K. Cheung, John Wawrzynek
2010	—	`conf`	Process Variability and Degradation: New Frontier for Reconfigurable. ARC Peter Y. K. Cheung
2010	—	`conf`	Towards anthropomorphic robot Thereminist. ROBIO Yan Wu, Polake Kuvinichkul, Peter Y. K. Cheung, Yiannis Demiris
2010	J	`jnl`	Wave-pipelined intra-chip signaling for on-FPGA communications. Integr. Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2009	Misc	`conf`	A DP-network for optimal dynamic routing in network-on-chip. CODES+ISSS Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam
2009	B	`conf`	A sensor-based approach to linear blur identification for real-time video enhancement. ICIP Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung
2009	B	`conf`	Area estimation and optimisation of FPGA routing fabrics. FPL Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2009	Misc	`conf`	Benchmarking Reconfigurable Architectures in the Mobile Domain. FCCM Peter Jamieson, Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Tero Rissa, Teemu Pitkänen
2009	J	`jnl`	Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2009	B	`conf`	Compensating for variability in FPGAs by re-mapping and re-placement. FPL N. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung
2009	—	`conf`	Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design. FPT Alastair M. Smith, George A. Constantinides, Steven J. E. Wilton, Peter Y. K. Cheung
2009	J	`jnl`	Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems. IET Comput. Digit. Tech. Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2009	J	`jnl`	Hardware architectures for eigenvalue computation of real symmetric matrices. IET Comput. Digit. Tech. Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung
2009	—	`conf`	Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep. ARC Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung
2009	J	`jnl`	High-throughput one-dimensional median and weighted median filters on FPGA. IET Comput. Digit. Tech. Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk
2009	—	`conf`	Parametric Design for Reconfigurable Software-Defined Radio. ARC Tobias Becker, Wayne Luk, Peter Y. K. Cheung
2009	A	`conf`	Partition-based exploration for reconfigurable JPEG designs. DATE Philip G. Potter, Wayne Luk, Peter Y. K. Cheung
2009	A	`ed.`	Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009 FPGA Paul Chow, Peter Y. K. Cheung
2009	J	`jnl`	Robust Real-Time Super-Resolution on FPGA and an Application to Video Enhancement. ACM Trans. Reconfigurable Technol. Syst. Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides
2009	J	`jnl`	Self-Measurement of Combinatorial Circuit Delays in FPGAs. ACM Trans. Reconfigurable Technol. Syst. Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung
2009	J	`jnl`	Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs. ACM Trans. Reconfigurable Technol. Syst. Christos-Savvas Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung
2009	C	`conf`	Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing. ISCAS Li Wang, Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung
2009	J	`jnl`	Word-length selection for power minimization via nonlinear optimization. ACM Trans. Design Autom. Electr. Syst. Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung
2008	—	`conf`	A transition probability based delay measurement method for arbitrary circuits on FPGAs. FPT Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung
2008	J	`jnl`	Affective Level Video Segmentation by Utilizing the Pleasure-Arousal-Dominance Information. IEEE Trans. Multim. Sutjipto Arifin, Peter Y. K. Cheung
2008	—	`conf`	Characterisation of FPGA Clock Variability. ISVLSI N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung
2008	—	`conf`	Co-optimisation of datapath and memory in outer loop pipelining. FPT Kieron Turkington, George A. Constantinides, Peter Y. K. Cheung, Konstantinos Masselos
2008	B	`conf`	Combating process variation on FPGAS with a precise at-speed delay measurement method. FPL Justin S. J. Wong, Peter Y. K. Cheung, N. Pete Sedcole
2008	B	`conf`	Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. FPL Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2008	J	`jnl`	Comments on the BCS Lecture "The Future of Computer Technology and its Implications for the Computer Industry" by Professor Steve Furber. Comput. J. Peter Y. K. Cheung, Alexandre Yakovlev
2008	—	`conf`	Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation. BCS Int. Acad. Conf. Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2008	J	`jnl`	Custom parallel caching schemes for hardware-accelerated image compression. J. Real Time Image Process. Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung
2008	—	`conf`	FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor. ARC Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides
2008	B	`conf`	Fault tolerant methods for reliability in FPGAs. FPL Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung
2008	C	`conf`	Glitch-aware output switching activity from word-level statistics. ISCAS Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung, Alastair M. Smith
2008	—	`conf`	Global interconnections in FPGAs: modeling and performance analysis. SLIP Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk
2008	A	`conf`	High-throughput interconnect wave-pipelining for global communication in FPGAs. FPGA Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2008	J	`jnl`	Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs. J. Signal Process. Syst. Maria E. Angelopoulou, Kostas Masselos, Peter Y. K. Cheung, Yiannis Andreopoulos
2008	—	`conf`	Implementation of Wave-Pipelined Interconnects in FPGAs. NOCS Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk
2008	J	`jnl`	Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices. IEEE Trans. Very Large Scale Integr. Syst. Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2008	—	`conf`	Interconnection lengths and delays estimation for communication links in FPGAs. SLIP Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2008	A	`conf`	Measuring and modeling FPGA clock variability. FPGA N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung
2008	—	`conf`	Modelling and compensating for clock skew variability in FPGAs. FPT N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung
2008	J	`jnl`	Outer Loop Pipelining for Application Specific Datapaths in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung
2008	J	`jnl`	Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations. ACM Trans. Reconfigurable Technol. Syst. N. Pete Sedcole, Peter Y. K. Cheung
2008	—	`conf`	Systematic design space exploration for customisable multi-processor architectures. ICSAMOS Ben Cope, Peter Y. K. Cheung, Wayne Luk
2008	B	`conf`	Towards benchmarking energy efficiency of reconfigurable architectures. FPL Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa
2008	A	`conf`	Using Reconfigurable Logic to Optimise GPU Memory Accesses. DATE Ben Cope, Peter Y. K. Cheung, Wayne Luk
2008	B	`conf`	Video enhancement on an adaptive image sensor. ICIP Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung
2008	—	`conf`	Wave-pipelined signaling for on-FPGA communication. FPT Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2007	—	`conf`	A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. NOCS Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam
2007	Misc	`conf`	A Hybrid Memory Sub-system for Video Coding Applications. FCCM Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung
2007	—	`conf`	A Novel Probabilistic Approach to Modeling the Pleasure-Arousal-Dominance Content of the Video based on "Working Memory". ICSC Sutjipto Arifin, Peter Y. K. Cheung
2007	—	`conf`	A Novel Video Parsing Algorithm Utilizing the Pleasure-Arousal-Dominance Emotional Information. ICIP (6) Sutjipto Arifin, Peter Y. K. Cheung
2007	A*	`conf`	A computation method for video segmentation utilizing the pleasure-arousal-dominance emotional information. ACM Multimedia Sutjipto Arifin, Peter Y. K. Cheung
2007	Misc	`conf`	Automatic On-chip Memory Minimization for Data Reuse. FCCM Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2007	—	`conf`	Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective. ASAP Ben Cope, Peter Y. K. Cheung, Wayne Luk
2007	Misc	`conf`	Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs. FCCM Christos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung
2007	B	`conf`	Efficient mapping of a Kalman filter into an FPGA using Taylor Expansion. FPL Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung
2007	Misc	`conf`	Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration. FCCM Tobias Becker, Wayne Luk, Peter Y. K. Cheung
2007	—	`conf`	Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction. FPT Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2007	B	`conf`	On the feasibility of early routing capacitance estimation for FPGAs. FPL Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung
2007	A	`conf`	Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis. FPGA N. Pete Sedcole, Peter Y. K. Cheung
2007	J	`jnl`	ROM to DSP block transfer for resource constrained synthesis. IET Comput. Digit. Tech. Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung
2007	J	`jnl`	Real-time hardware acceleration of the trace transform. J. Real Time Image Process. Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk
2007	J	`jnl`	Run-Time Integration of Reconfigurable Video Processing Systems. IEEE Trans. Very Large Scale Integr. Syst. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2007	—	`conf`	Self-characterization of Combinatorial Circuit Delays in FPGAs. FPT Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung
2006	—	`conf`	A Flexible Multi-port Caching Scheme for Reconfigurable Platforms. ARC Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2006	B	`conf`	A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design. FPL Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2006	Misc	`conf`	A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design. FCCM Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2006	B	`conf`	A Spatiotemporal Saliency Framework. ICIP Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung
2006	—	`conf`	A comparison of 2-D discrete wavelet transform computation schedules on FPGAs. FPT Maria E. Angelopoulou, Konstantinos Masselos, Peter Y. K. Cheung, Yiannis Andreopoulos
2006	—	`conf`	A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentation. DATE Designers' Forum Sutjipto Arifin, Peter Y. K. Cheung
2006	—	`conf`	A statistical framework for dimensionality reduction implementation in FPGAs. FPT Christos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung
2006	B	`conf`	Efficient Realtime FPGA Implementation of the Trace Transform. FPL Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk
2006	B	`conf`	FPGA-Accelerated Pre-Attentive Segmentation in Primary Visual Cortex. FPL Christos-Savvas Bouganis, Peter Y. K. Cheung, Zhaoping Li
2006	C	`conf`	Fast word-level power models for synthesis of FPGA-based arithmetic. ISCAS Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides, Peter Y. K. Cheung
2006	A	`conf`	Hardware efficient architectures for Eigenvalue computation. DATE Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung, Philip Heng Wai Leong, Stephen J. Motley
2006	—	`conf`	On-Chip Communication in Run-Time Assembled Reconfigurable Systems. ICSAMOS N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2006	B	`conf`	On-FPGA Communication Architectures and Design Factors. FPL Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2006	J	`jnl`	Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits. IEEE Trans. Circuits Syst. II Express Briefs Gabriel Caffarena, George A. Constantinides, Peter Y. K. Cheung, Carlos Carreras, Octavio Nieto-Taladriz
2006	B	`conf`	Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. FPL Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
2006	—	`conf`	The cost of data dependence in motion vector estimation for reconfigurable platforms. FPT Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung
2006	B	`conf`	Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling System. FPL Sutjipto Arifin, Peter Y. K. Cheung
2006	B	`conf`	User Attention Based Arousal Content Modeling. ICIP Sutjipto Arifin, Peter Y. K. Cheung
2006	—	`conf`	Within-die delay variability in 90nm FPGAs and beyond. FPT N. Pete Sedcole, Peter Y. K. Cheung
2006	A	`conf`	Yield enhancements of design-specific FPGAs. FPGA Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
2005	Misc	`conf`	A Novel 2D Filter Design Methodology for Heterogeneous Devices. FCCM Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung
2005	—	`conf`	A heuristic approach for multiple restricted multiplication. ISCAS (1) Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
2005	—	`conf`	A novel 2D filter design methodology. ISCAS (1) Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung
2005	B	`conf`	An Analytical Approach to Generation and Exploration of Reconfigurable Architectures. FPL Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2005	A	`conf`	Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. FPGA Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
2005	Misc	`conf`	Automating custom-precision function evaluation for embedded processors. CASES Ray C. C. Cheung, Dong-U Lee, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung
2005	—	`conf`	Cell Based Motion Estimators for Reconfigurable Platforms. ERSA Wim J. C. Melis, Kieron Turkington, Alexander Whitton, Wayne Luk, Peter Y. K. Cheung, Paul Metzgen
2005	J	`jnl`	Customizable elliptic curve cryptosystems. IEEE Trans. Very Large Scale Integr. Syst. Ray C. C. Cheung, N. J. Telle, Wayne Luk, Peter Y. K. Cheung
2005	B	`conf`	Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic. FPL Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides
2005	A	`conf`	Exploration of heterogeneous reconfigurable architectures (abstract only). FPGA Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2005	—	`conf`	FPGA Based Router for Cognitive Packet Networks. FPT Laurence A. Hey, Peter Y. K. Cheung, Michael Gellman
2005	A	`conf`	Hardware Acceleration of Hidden Markov Model Decoding for Person Detection. DATE Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk
2005	J	`jnl`	Hardware/software codesign: a systematic approach targeting data-intensive applications. IEEE Signal Process. Mag. Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
2005	—	`conf`	Have GPUs Made FPGAs Redundant in the Field of Video Processing? FPT Ben Cope, Peter Y. K. Cheung, Wayne Luk, Sarah Witt
2005	B	`conf`	Heterogeneity Exploration for Multiple 2D Filter Designs. FPL Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides
2005	B	`conf`	Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing. FPL Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk
2005	J	`jnl`	Optimum and heuristic synthesis of multiple word-length architectures. IEEE Trans. Very Large Scale Integr. Syst. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2005	B	`conf`	Power and Area Optimization for Multiple Restricted Multiplication. FPL Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
2005	A	`conf`	Reconfigurable Elliptic Curve Cryptosystems on a Chip. DATE Ray C. C. Cheung, Wayne Luk, Peter Y. K. Cheung
2005	B	`conf`	Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow. FPL Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung
2005	B	`conf`	Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes. FPL Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
2004	J	`jnl`	A Gaussian Noise Generator for Hardware-Based Simulations. IEEE Trans. Computers Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
2004	A	`conf`	A Novel Implementation of Tile-Based Address Mapping. DATE Sambuddhi Hettiaratchi, Peter Y. K. Cheung
2004	B	`conf`	A Steerable Complex Wavelet Construction and Its Implementation on FPGA. FPL Christos-Savvas Bouganis, Peter Y. K. Cheung, Jeffrey Ng, Anil A. Bharath
2004	B	`conf`	A Structured Methodology for System-on-an-FPGA Design. FPL N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2004	Misc	`conf`	A Structured System Methodology for FPGA Based System-on-A-Chip Design. FCCM N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2004	—	`conf`	A scalable hardware architecture for prime number validation. FPT Ray C. C. Cheung, Ashley Brown, Wayne Luk, Peter Y. K. Cheung
2004	—	`conf`	Autonomous Memory Block for reconfigurable computing. ISCAS (2) Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk
2004	B	`conf`	BIST Based Interconnect Fault Location for FPGAs. FPL Nicola Campregher, Peter Y. K. Cheung, Milan Vasilko
2004	—	`conf`	Distinguished Paper: Automated Combination of Simulation and Hardware Prototyping. ERSA Tero Rissa, Wayne Luk, Peter Y. K. Cheung
2004	B	`conf`	Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation. FPL Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides
2004	J	`jnl`	Guest Editors' Introduction: Field Programmable Logic and Applications. IEEE Trans. Computers Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa
2004	Misc	`conf`	Migrating Functionality from ROMS to Embedded Multipliers. FCCM Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung
2004	B	`conf`	Multiple Restricted Multiplication. FPL Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
2004	—	`conf`	Scalable structured data access by combining autonomous memory blocks. FPT Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk
2004	B	`conf`	SoftSONIC: A Customisable Modular Platform for Video Applications. FPL Tero Rissa, Peter Y. K. Cheung, Wayne Luk
2004	—	`book`	Synthesis and optimization of DSP algorithms. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2004	Misc	`conf`	Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs. FCCM Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung
2003	Misc	`conf`	A Hardware Gaussian Noise Generator for Channel Code Evaluation. FCCM Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
2003	B	`conf`	A Reconfigurable Platform for Real-Time Embedded Video Image Processing. FPL N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2003	B	`conf`	A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer. FPL Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
2003	—	`conf`	Architectures for function evaluation on FPGAs. ISCAS (2) Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
2003	B	`conf`	Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System. FPL Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
2003	B	`ed.`	Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings FPL Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa
2003	B	`conf`	Globally Asynchronous Locally Synchronous FPGA Architectures. FPL Andrew Royal, Peter Y. K. Cheung
2003	—	`conf`	Hierarchical segmentation schemes for function evaluation. FPT Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
2003	—	`conf`	High-level language extensions for run-time reconfigurable systems. FPT T. K. Lee, Arran Derbyshire, Wayne Luk, Peter Y. K. Cheung
2003	A	`conf`	Mesh Partitioning Approach to Energy Efficient Data Layout. DATE Sambuddhi Hettiaratchi, Peter Y. K. Cheung
2003	—	`conf`	Multitasking in hardware-software codesign for reconfigurable computer. ISCAS (5) Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
2003	B	`conf`	Non-uniform Segmentation for Hardware Function Evaluation. FPL Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
2003	—	`conf`	SONICmole: a debugging environment for the UltraSONIC reconfigurable computer. ISCAS (2) Theerayod Wiangtong, Chun Te Ewe, Peter Y. K. Cheung
2003	J	`jnl`	Synthesis of saturation arithmetic architectures. ACM Trans. Design Autom. Electr. Syst. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2003	J	`jnl`	Wordlength optimization for linear digital signal processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2002	B	`conf`	Automating Customisation of Floating-Point Designs. FPL Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi, James Hwang
2002	J	`jnl`	Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware-Software Codesign. Des. Autom. Embed. Syst. Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
2002	Misc	`conf`	Customising Floating-Point Designs. FCCM Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi
2002	A	`conf`	Energy efficient address assignment through minimized memory row switching. ICCAD Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke
2002	—	`conf`	Floating-point bitwidth analysis via automatic differentiation. FPT Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi
2002	B	`conf`	Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer. FPL Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk
2002	Misc	`conf`	Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform. FCCM Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk
2002	—	`conf`	Incremental programming for reconfigurable engines. FPT Dong-U Lee, T. K. Lee, Wayne Luk, Peter Y. K. Cheung
2002	Misc	`conf`	Optimum Wordlength Allocation. FCCM George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2002	—	`conf`	PD-XML: extensible markup language for processor description. FPT Shay Ping Seng, Krishna V. Palem, Rodric M. Rabbah, Weng-Fai Wong, Wayne Luk, Peter Y. K. Cheung
2002	A	`conf`	Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory. DATE Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke
2002	Misc	`conf`	Reconfigurable Shape-Adaptive Template Matching Architectures. FCCM Jörn Gause, Peter Y. K. Cheung, Wayne Luk
2002	B	`conf`	Run-Time Adaptive Flexible Instruction Processors. FPL Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung
2002	—	`conf`	Strassen's matrix multiplication for customisable processors. FPT Henry M. D. Ip, James D. Low, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk, Shay Ping Seng, Paul Metzgen
2002	Misc	`conf`	Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software Codesign. FCCM Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
2001	B	`conf`	A Digit-Serial Structure for Reconfigurable Multipliers. FPL Chakkapas Visavakul, Peter Y. K. Cheung, Wayne Luk
2001	A	`conf`	Heuristic datapath allocation for multiple wordlength systems. DATE George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2001	—	`conf`	MASH delta-sigma modulators for wideband and multi-standard applications. ISCAS (4) Kei-Tee Tiew, Alison J. Payne, Peter Y. K. Cheung
2001	J	`jnl`	Quantitative Analysis of FPGA-based Database Searching. J. VLSI Signal Process. Nabeel Shirazi, Dan Benyamin, Wayne Luk, Peter Y. K. Cheung, Shaori Guo
2001	Misc	`conf`	The Effect of FPGA Granularity on Video Codec Implementations. FCCM Jörn Gause, Carsten Reuter, Holger Kropp, Peter Y. K. Cheung, Wayne Luk
2001	Misc	`conf`	The Multiple Wordlength Paradigm. FCCM George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2000	Misc	`conf`	Flexible instruction processors. CASES Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung
2000	Misc	`conf`	Multiple Precision for Resource Minimization. FCCM George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2000	B	`conf`	Multiple-Wordlength Resource Binding. FPL George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2000	C	`conf`	Roundoff-noise shaping in filter design. ISCAS George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2000	B	`conf`	Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT. FPL Jörn Gause, Peter Y. K. Cheung, Wayne Luk
2000	J	`jnl`	Video Image Processing with the Sonic Architecture. Computer Simon D. Haynes, John Stone, Peter Y. K. Cheung, Wayne Luk
1999	—	`conf`	Flexible reconfigurable multiplier blocks suitable for enhancing the architecture of FPGAs. CICC Simon D. Haynes, Antonio B. Ferrari, Peter Y. K. Cheung
1999	B	`conf`	Quantitative Analysis of Run-Time Reconfigurable Database Search. FPL Nabeel Shirazi, Wayne Luk, Dan Benyamin, Peter Y. K. Cheung
1999	Misc	`conf`	Reconfigurable Computing for Augmented Reality. FCCM Wayne Luk, T. K. Lee, J. Rice, Nabeel Shirazi, Peter Y. K. Cheung
1999	Misc	`conf`	SONIC - A Plug-In Architecture for Video Processing. FCCM Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone
1999	B	`conf`	SONIC - A Plug-In Architecture for Video Processing. FPL Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone
1998	Misc	`conf`	A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure. FCCM Simon D. Haynes, Peter Y. K. Cheung
1998	—	`conf`	Algorithms and Structures for Reconfigurable Multiplication Units. SBCCI Simon D. Haynes, Antonio B. Ferrari, Peter Y. K. Cheung
1998	Misc	`conf`	Automating Production of Run-Time Reconfigurable Designs. FCCM Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung
1998	B	`conf`	Run-Time Management of Dynamically Recongigurable Designs. FPL Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung
1997	—	`conf`	A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems. ASYNC Pedro A. Molina, Peter Y. K. Cheung
1997	B	`conf`	A reconfigurable data-localised array for morphological algorithms. FPL Anjit Sekhar Chaudhuri, Peter Y. K. Cheung, Wayne Luk
1997	C	`conf`	Asnchronous Wrapper for Heterogeneous Systems. ICCD David S. Bormann, Peter Y. K. Cheung
1997	Misc	`conf`	Compilation tools for run-time reconfigurable designs. FCCM Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung
1997	J	`jnl`	Diagnosis of Boards for Realistic Interconnect Shorts. J. Electron. Test. José T. de Sousa, Peter Y. K. Cheung
1997	B	`ed.`	Field-Programmable Logic and Applications, 7th International Workshop, FPL '97, London, UK, September 1-3, 1997, Proceedings FPL Wayne Luk, Peter Y. K. Cheung, Manfred Glesner
1997	—	`conf`	Improved diagnosis of realistic interconnect shorts. ED&TC José T. de Sousa, Peter Y. K. Cheung
1997	J	`jnl`	Modelling and Handling Uncertainties in Mobile Robotics. J. Intell. Fuzzy Syst. Majd Alwan, Peter Y. K. Cheung
1997	B	`conf`	Pipeline morphing and virtual pipelines. FPL Wayne Luk, Nabeel Shirazi, Shaori Guo, Peter Y. K. Cheung
1997	B	`conf`	Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research. FPL Patrick I. Mackinlay, Peter Y. K. Cheung, Wayne Luk, Richard Sandiford
1996	B	`conf`	Adaptive Automatic Facial Feature Segmentation. FG Hasan Demirel, Thomas J. Clarke, Peter Y. K. Cheung
1996	—	`conf`	An incremental machine learning mechanism applied to robot navigation. ANZIIS Nawwaf N. Kharma, Majd Alwan, Peter Y. K. Cheung
1996	—	`conf`	Combining goal-directed, reactive and reflexive navigation in autonomous mobile robots. ANZIIS Majd Alwan, Peter Y. K. Cheung, Akram Saleh, Nour E. Cheikh Obeid
1996	J	`jnl`	Hierarchical tolerance analysis using statistical behavioral models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Timo Koskinen, Peter Y. K. Cheung
1996	Misc	`conf`	Modelling and optimising run-time reconfigurable systems. FCCM Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung
1996	Misc	`conf`	On the viability of FPGA-based integrated coprocessors. FCCM Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke
1996	—	`conf`	Realistic Fault Extraction for Boards. ED&TC José T. de Sousa, T. Shen, Peter Y. K. Cheung
1994	C	`conf`	A Method of Representative Fault Selection in Digital Circuits for ATPG. ISCAS Akachai Sang-In, Peter Y. K. Cheung
1994	—	`conf`	A Model-based Approach to Analog Fault Diagnosis using Techniques from Optimisation. EDAC-ETC-EUROASIC Salman Ahmed, Peter Y. K. Cheung, Phil Collins
1994	C	`conf`	Analog Fault Diagnosis - A Practical Approach. ISCAS Salman Ahmed, Peter Y. K. Cheung
1994	C	`conf`	Area & Time Limitations of FPGA-based Virtual Hardware. ICCD Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke
1994	C	`conf`	Virtual Hardware and the Limits of Computational Speed-up. ISCAS Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke
1993	C	`conf`	A New Schematic-driven Floorplanning Algorithm for Analog Cell Layout. ISCAS Nasir-ud-Din Gohar, Peter Y. K. Cheung
1991	C	`conf`	A Tag Coprocessor Architecture for Symbolic Languages. ICCD Vicente Fuentes-Sánchez, Peter Y. K. Cheung
1991	—	`conf`	Model-based fault diagnosis of sequential circuits and its acceleration. EURO-DAC Benjamin Rogel-Favila, Antony Wakeling, Peter Y. K. Cheung