Peter Wohl - RankMe

43 papers A* 5A 21B 1Misc 9Journal 2Unranked 5

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Hybrid Static Learning for ATPG. ITC Jonathon E. Colburn, Peter Wohl, John A. Waicukauski, Yasunari Kanzawa
2025	—	`conf`	Improving ATPG through Abort-Driven Dynamic Learning (ADDLe). ITC-Asia Peter Wohl, John A. Waicukauski, Jonathon E. Colburn, Yasunari Kanzawa
2018	A	`conf`	XLBIST: X-Tolerant Logic BIST. ITC Peter Wohl, John A. Waicukauski, Gregory A. Maston, Jonathon E. Colburn
2017	A*	`conf`	A New Paradigm for Synthesis of Linear Decompressors. DAC Emil Gizdarski, Peter Wohl, John A. Waicukauski
2014	A	`conf`	Achieving extreme scan compression for SoC Designs. ITC Peter Wohl, John A. Waicukauski, Jonathon E. Colburn, Milind Sonawane
2014	A	`conf`	Fault sharing in a copy-on-write based ATPG system. ITC X. Cai, Peter Wohl, Daniel Martin
2013	A	`conf`	A distributed-multicore hybrid ATPG system. ITC X. Cai, Peter Wohl
2013	Misc	`conf`	Improving test generation by use of majority gates. VTS Peter Wohl, John A. Waicukauski
2013	A	`conf`	Two-level compression through selective reseeding. ITC Peter Wohl, John A. Waicukauski, Frederic Neuveux, Gregory A. Maston, Nadir Achouri, Jonathon E. Colburn
2012	Misc	`conf`	Enhancing testability by structured partial scan. VTS Peter Wohl, John A. Waicukauski, Jonathon E. Colburn
2012	A	`conf`	Hybrid selector for high-X scan compression. ITC Peter Wohl, John A. Waicukauski, Frederic Neuveux, Jonathon E. Colburn
2010	A*	`conf`	Fully X-tolerant, very high scan compression. DAC Peter Wohl, John A. Waicukauski, Frederic Neuveux, Emil Gizdarski
2010	A	`conf`	Highly efficient parallel ATPG based on shared memory. ITC X. Cai, Peter Wohl, John A. Waicukauski, Pramod Notiyath
2010	A	`conf`	Increasing PRPG-based compression by delayed justification. ITC Peter Wohl, John A. Waicukauski, T. Finklea
2008	A	`conf`	Increasing Scan Compression by Using X-chains. ITC Peter Wohl, John A. Waicukauski, Frederic Neuveux
2007	Misc	`conf`	Automated Design and Insertion of Optimal One-Hot Bus Encoders. VTS Peter Wohl, John A. Waicukauski, Sanjay Patel
2007	J	`jnl`	DFT MAX and Power. J. Low Power Electron. Rohit Kapur, T. Finklea, Felix Ng, Anshuman Chandra, Sanjay Ramnath, Peter Wohl, Thomas W. Williams, Ashok Anbalan, Sandeep S. Kulkarni, Tammy Fernandes, Pramod Notiyath, Rajesh Uppuluri
2007	A	`conf`	Fully X-tolerant combinational scan compression. ITC Peter Wohl, John A. Waicukauski, Sanjay Ramnath
2007	Misc	`conf`	Minimizing the Impact of Scan Compression. VTS Peter Wohl, John A. Waicukauski, Rohit Kapur, Sanjay Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini
2005	A	`conf`	Efficient compression of deterministic patterns into multiple PRPG seeds. ITC Peter Wohl, John A. Waicukauski, Sanjay Patel, Francisco DaSilva, Thomas W. Williams, Rohit Kapur
2005	Misc	`conf`	Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST. VTS Peter Wohl, John A. Waicukauski, Sanjay Patel, Cy Hay, Emil Gizdarski, Ben Mathew
2004	A*	`conf`	Scalable selector architecture for x-tolerant deterministic BIST. DAC Peter Wohl, John A. Waicukauski, Sanjay Patel
2003	Misc	`conf`	Analysis and Design of Optimal Combinational Compactors. VTS Peter Wohl, Leendert M. Huisman
2003	A*	`conf`	Efficient compression and application of deterministic patterns in a logic BIST architecture. DAC Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin
2003	A	`conf`	X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture. ITC Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin
2002	A*	`conf`	Effective diagnostics through interval unloads in a BIST environment. DAC Peter Wohl, John A. Waicukauski, Sanjay Patel, Gregory A. Maston
2001	A	`conf`	Design of compactors for signature-analyzers in built-in self-test. ITC Peter Wohl, John A. Waicukauski, Thomas W. Williams
2000	A	`conf`	Optimizing the flattened test-generation model for very large designs. ITC Peter Wohl, John A. Waicukauski
2000	Misc	`conf`	P1450.1: STIL for the Simulation Environmen. VTS Peter Wohl, Nathan Biggs
1999	A	`conf`	Output in still, input in still. ITC Peter Wohl
1999	A	`conf`	Using Verilog simulation libraries for ATPG. ITC Peter Wohl, John A. Waicukauski
1998	A	`conf`	Defining ATPG rules checking in STIL. ITC Peter Wohl, John A. Waicukauski
1998	A	`conf`	Extracting gate-level networks from simulation tables. ITC Peter Wohl, John A. Waicukauski
1997	A	`conf`	A Unified Interface for Scan Test Generation Based on STIL. ITC Peter Wohl, John A. Waicukauski
1997	Misc	`conf`	Using ATPG for clock rules checking in complex scan design. VTS Peter Wohl, John A. Waicukauski
1996	A	`conf`	Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates. ITC Peter Wohl, John A. Waicukauski
1996	Misc	`conf`	Testing "untestable" faults in three-state circuits. VTS Peter Wohl, John A. Waicukauski, Matthew Graf
1993	J	`jnl`	Efficiency through Reduced Communication in Message Passing Simulation of Neural Networks. Int. J. Artif. Intell. Tools Peter Wohl
1992	—	`conf`	Designing Conceptual Clustering for Parallel Implementation. ICPP (3) Peter Wohl, Thomas W. Christopher
1991	—	`conf`	A Parallel Processing Approach to Incremental Conceptual Clustering. IPPS Peter Wohl, Thomas W. Christopher
1991	B	`conf`	MIMD implementation of neural networks through pipelined, parallel communication trees. ICTAI Peter Wohl, Thomas W. Christopher
1991	—	`conf`	Parallel Conceptual Clustering through Message-Driven Computing. ICPP (2) Peter Wohl, Thomas W. Christopher
1990	—	`conf`	SIMD Neural Net Mapping on MIMD Architectures. ICPP (1) Peter Wohl, Thomas W. Christopher