Peter Suaris - RankMe

14 papers A* 4A 6Journal 1Unranked 3

Year	Rank	Type	Title / Venue / Authors
2007	J	`jnl`	Efficient Timing Analysis With Known False Paths Using Biclique Covering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng
2005	—	`conf`	A practical cut-based physical retiming algorithm for field programmable gate arrays. ASP-DAC Peter Suaris, Dongsheng Wang, Nan-Chi Chou
2005	A	`conf`	Improving the efficiency of static timing analysis with false paths. ICCAD Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris
2005	A	`conf`	The effect of post-layout pin permutation on timing. FPGA Yuzheng Ding, Peter Suaris, Nan-Chi Chou
2005	A	`conf`	Total power-optimal pipelining and parallel processing under process variations in nanometer technology. ICCAD Peter Suaris, Taeho Kgil, Keith A. Bowman, Vivek De, Trevor N. Mudge
2005	—	`conf`	Unified quadratic programming approach for mixed mode placement. ISPD Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris
2004	A	`conf`	Fast adders in modern FPGAs. FPGA Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris
2004	A	`conf`	Incremental physical resynthesis for timing optimization. FPGA Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou
2003	—	`conf`	A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages. PATMOS Dongsheng Wang, Peter Suaris, Nan-Chi Chou
2003	A	`conf`	A physical retiming algorithm for field programmable gate arrays. FPGA Peter Suaris, Dongsheng Wang, Pei-Ning Guo, Nan-Chi Chou
2003	A*	`conf`	An algebraic multigrid solver for analytical placement with layout based clustering. DAC Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu
2000	A*	`conf`	Fast post-placement rewiring using easily detectable functional symmetries. DAC Chih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska
1997	A*	`conf`	Interface Timing Verification Drives System Design. DAC Ajay J. Daga, Peter Suaris
1994	A*	`conf`	A Methodology and Algorithms for Post-Placement Delay Optimization. DAC Lalgudi N. Kannan, Peter Suaris, Hong-Gee Fang