Peter Poechmueller

14 papers B 3Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2025 B conf
Silent Data Corruption: DRAM Root Causes and Ways of Improving Test Quality Towards 0ppm.
ETS
Chenyu Fang, Peter Poechmueller
2024 B conf
Semiconductor Application Fail Root Causes And Secure Test Remedy.
ETS
Heguo Yin, Peter Poechmueller
2023 J jnl
A 55-nm Three-Stage Operational Transconductance Amplifier With Single Cascode Miller Compensation for Large Capacitive Loads.
IEEE Trans. Very Large Scale Integr. Syst.
Ranran Zhou, Haozhe Wang, Peng Wang, Peter Poechmueller, Yong Wang
2022 J jnl
An Analog Circuit Design and Optimization System With Rule-Guided Genetic Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ranran Zhou, Peter Poechmueller, Yong Wang
1999 J jnl
A 390-mm
IEEE J. Solid State Circuits
Toshiaki Kirihata, Gerhard Mueller, Brian Ji, Gerd Frankowsky, Joseph M. Ross, Hartmud Terletzki, Dmitry G. Netis, Oliver Weinfurtner, David R. Hanson, Gabriel Daniel, Louis Lu-Chen Hsu, Daniel W. Storaska, Armin M. Reith, Marco A. Hug, Kevin P. Guay, Manfred Selz, Peter Poechmueller, Heinz Hoenigschmid, Matthew R. Wordeman
1996 J jnl
A 286 mm
IEEE J. Solid State Circuits
Yohji Watanabe, Ring Wong, Toshiaki Kirihata, Daisuke Kato, John K. DeBrosse, Takahiko Rara, Munehiro Yoshida, Rideo Mukai, Khandker N. Quader, Takeshi Nagai, Peter Poechmueller, Peter Pfefferl, Matthew R. Wordeman, Shuso Fujii
1996 J jnl
Fault-tolerant designs for 256 Mb DRAM.
IEEE J. Solid State Circuits
Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida, Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke, Yoshiaki Asao
1993 — conf
High-level synthesis transformations for programmable architectures.
EURO-DAC
Peter Poechmueller, Manfred Glesner, Fang Longsen
1992 B conf
High Level Synthesis in an FPL-Based Computer Aided Prototyping Environment.
FPL
Peter Poechmueller, Hans-Jürgen Herpel, Manfred Glesner, Fang Longsen
1992 — conf
High-level synthesis in a rapid-prototype environment for mechatronic systems.
EURO-DAC
Norbert Wehn, Hans-Jürgen Herpel, Thomas Hollstein, Peter Poechmueller, Manfred Glesner
1991 — conf
A CAD tool for designing large, fault-tolerant VLSI arrays.
Great Lakes Symposium on VLSI
Peter Poechmueller, G. K. Sharma, Manfred Glesner
1991 — conf
A New Approach for Designing Fault-Tolerant Array Processors.
Fault-Tolerant Computing Systems
Peter Poechmueller, Manfred Glesner
1991 — conf
An approach for multilevel logic cell optimization in module generators.
Great Lakes Symposium on VLSI
Peter Poechmueller, Manfred Glesner
1991 — conf
HADES-high-level architecture development and exploration system.
Great Lakes Symposium on VLSI
Peter Poechmueller, Michael Held, Norbert Wehn, Manfred Glesner