Peter Pirsch - RankMe

120 papers A* 2A 4B 3C 19Misc 7Journal 32Unranked 49

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	Continuous-Flow Matrix Transposition Using Memories. IEEE Trans. Circuits Syst. I Regul. Pap. Mario Garrido, Peter Pirsch
2017	—	`conf`	High Performance and Low Power Architectures: GPU vs. FPGA for Fast Factorized Backprojection. CANDAR M. Wielage, Fabian Cholewa, Christian Fahnemann, Peter Pirsch, Holger Blume
2016	—	`conf`	An FPGA architecture for velocity independent backprojection in FMCW-based SAR systems. ISSPIT Fabian Cholewa, M. Wielage, Peter Pirsch, Holger Blume
2013	—	`ch.`	Architectures for Stereo Vision. Handbook of Signal Processing Systems Christian Banz, Holger Blume, Peter Pirsch
2013	J	`jnl`	Using SDRAM Memories for High-Performance Accesses to Two-Dimensional Matrices Without Transpose. Int. J. Parallel Program. Stefan Langemeyer, Peter Pirsch, Holger Blume
2011	Misc	`conf`	A FPGA architecture for real-time processing of variable-length FFTS. ICASSP Stefan Langemeyer, Peter Pirsch, Holger Blume
2011	—	`conf`	Real-time semi-global matching disparity estimation on the GPU. ICCV Workshops Christian Banz, Holger Blume, Peter Pirsch
2011	—	`conf`	Using SDRAMs for two-dimensional accesses of long 2 ICSAMOS Stefan Langemeyer, Peter Pirsch, Holger Blume
2010	J	`jnl`	A Multi-Shared Register File Structure for VLIW Processors. J. Signal Process. Syst. Guillermo Payá-Vayá, Javier Martín-Langerwerf, Peter Pirsch
2010	—	`conf`	A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architectures. ASAP Guillermo Payá-Vayá, Javier Martín-Langerwerf, Holger Blume, Peter Pirsch
2010	—	`conf`	A fully programmable FSM-based Processing Engine for Gigabytes/s header parsing. ICSAMOS Konstantin Septinus, Peter Pirsch, Holger Blume, Ulrich Mayer
2010	—	`conf`	Mapping of a Real-Time Object Detection Application onto a Configurable RISC/Coprocessor Architecture at Full HD Resolution. ReConFig Holger Flatt, Holger Blume, Peter Pirsch
2010	—	`conf`	Real-time stereo vision system using semi-global matching disparity estimation: Architecture and FPGA-implementation. ICSAMOS Christian Banz, Sebastian Hesselbarth, Holger Flatt, Holger Blume, Peter Pirsch
2009	—	`conf`	An Enhanced DMA Controller in SIMD Processors for Video Applications. ARCS Guillermo Payá-Vayá, Javier Martín-Langerwerf, Sören Moch, Peter Pirsch
2009	—	`conf`	Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures. ICSAMOS Holger Flatt, Ingo Schmädecke, Michael Kärgel, Holger Blume, Peter Pirsch
2009	—	`conf`	Instruction merging to increase parallelism in VLIW architectures. SoC Guillermo Payá-Vayá, Javier Martín-Langerwerf, Florian Giesemann, Holger Blume, Peter Pirsch
2009	—	`conf`	Memory efficient programmable processor for bitstream processing and entropy decoding of multiple-standard high-bitrate HDTV video bitstreams. SoCC Norman Nolte, Sören Moch, Markus Kock, Peter Pirsch
2008	—	`conf`	A parallel hardware architecture for connected component labeling based on fast label merging. ASAP Holger Flatt, Steffen Blume, Sebastian Hesselbarth, Torsten Schünemann, Peter Pirsch
2008	—	`conf`	On the Benefit of Caching Traffic Flow Data in the Link Buffer. SAMOS Konstantin Septinus, Christian Grimm, Vladislav Rumyantsev, Peter Pirsch
2007	—	`conf`	A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing. SAMOS Holger Flatt, Sebastian Hesselbarth, Sebastian Flügel, Peter Pirsch
2007	Misc	`conf`	ChipDesign: from theory to real world. WCAE Guillermo Payá-Vayá, Thomas Jambor, Konstantin Septinus, Sebastian Hesselbarth, Holger Flatt, Marc Freisfeld, Peter Pirsch
2007	—	`conf`	Design Space Exploration of Media Processors: A Generic VLIW Architecture and a Parameterized Scheduler. ARCS Guillermo Payá-Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch
2007	—	`conf`	Design Space Exploration of Media Processors: A Parameterized Scheduler. ICSAMOS Guillermo Payá-Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch
2007	—	`conf`	On the Design of Scalable Massively Parallel CRC Circuits. ICECS Konstantin Septinus, Thuyen Le, Ulrich Mayer, Peter Pirsch
2007	C	`conf`	RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip. DSD Guillermo Payá-Vayá, Javier Martín-Langerwerf, Peter Pirsch
2007	A	`conf`	Scalable Multi-Standard LSI Texture Encoder for MPEG and VC-1 Video Compression. ICME Norman Nolte, Winfried Gehrke, Frank Wiczinowski, Peter Pirsch
2006	C	`conf`	A Highly Parallel Sub-Pel Accurate Motion Estimator for H.264. MMSP Sebastian Flügel, Heiko Klußmann, Peter Pirsch, Marco Schulz, Malik Cisse, Winfried Gehrke
2005	J	`jnl`	A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications. J. VLSI Signal Process. Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch
2005	—	`conf`	A multi-core SoC design for advanced image and video compression. ICASSP (5) Andreas Dehnhardt, Mark Bernd Kulaczewski, Lars Friebe, Sören Moch, Peter Pirsch, Hans-Joachim Stolberg, Carsten Reuter
2005	C	`conf`	Architecture of a flexible on-board real-time SAR-processor. IGARSS Stefan Langemeyer, Christian Simon-Klar, Norman Nolte, Peter Pirsch
2005	J	`jnl`	HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing. J. VLSI Signal Process. Hans-Joachim Stolberg, Mladen Berekovic, Sören Moch, Lars Friebe, Mark Bernd Kulaczewski, Sebastian Flügel, Heiko Klußmann, Andreas Dehnhardt, Peter Pirsch
2005	—	`conf`	RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration. SAMOS Guillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch
2005	—	`conf`	Von abstrakten Architekturtemplates zur hardwarenahen Architekturexploration. GI Jahrestagung (1) Matthias Winter, Peter Pirsch
2004	J	`jnl`	A scalable, clustered SMT processor for digital signal processing. SIGARCH Comput. Archit. News Mladen Berekovic, Sören Moch, Peter Pirsch
2004	J	`jnl`	HIBRID-SOC: a multi-core architecture for image and video applications. SIGARCH Comput. Archit. News Sören Moch, Mladen Berekovic, Hans-Joachim Stolberg, Lars Friebe, Mark Bernd Kulaczewski, Andreas Dehnhardt, Peter Pirsch
2004	C	`conf`	Next generation on-board SAR processor for compact airborne systems. IGARSS Norman Nolte, Christian Simon-Klar, Stefan Langemeyer, Martin Kirscht, Peter Pirsch
2004	—	`conf`	Performance Estimation of Streaming Media Applications for Reconfigurable Platforms. SAMOS Carsten Reuter, Javier Martín-Langerwerf, Hans-Joachim Stolberg, Peter Pirsch
2003	C	`conf`	A compact and flexible multi-DSP system for real-time SAR applications. IGARSS Stefan Langemeyer, Helge Kloos, Christian Simon-Klar, Lars Friebe, Willm Hinrichs, Hanno Lieske, Peter Pirsch
2003	A	`conf`	A core for ambient and mobile intelligent imaging applications. ICME Jörn Jachalsky, Martin Wahler, Peter Pirsch, S. Capperon, Winfried Gehrke, W. M. Kruijtzer, Antonio Núñez
2003	A	`conf`	HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications. DATE Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Xun Mao, Mark Bernd Kulaczewski, Heiko Klußmann, Peter Pirsch
2003	C	`conf`	HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing. VLSI-SOC Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Mark Bernd Kulaczewski, Peter Pirsch
2003	—	`conf`	HiBRID-SoC: a multi-core architecture for image and video applications. ICIP (3) Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Mark Bernd Kulaczewski, Peter Pirsch
2002	—	`conf`	A flexible, fully configurable architecture for MPEG-2 video encoding. ICECS Jörn Jachalsky, M. Wahle, Peter Pirsch, Winfried Gehrke
2002	C	`conf`	A multi DSP board for real time SAR processing using the HiPAR-DSP 16. IGARSS Christian Simon-Klar, Lars Friebe, Helge Kloos, Hanno Lieske, Willm Hinrichs, Peter Pirsch
2002	—	`conf`	A platform-independent methodology for performance estimation of streaming media applications. ICME (2) Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch
2002	J	`jnl`	Architecture of an Image Rendering Co-Processor for MPEG-4 Visual Compositing. J. VLSI Signal Process. Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo
2002	C	`conf`	Benefits of Macro-Based Multi-FPGA Partitioning for Video Processing Applications. IEEE International Workshop on Rapid System Prototyping Javier Martín-Langerwerf, Carsten Reuter, Holger Kropp, Peter Pirsch
2002	Misc	`conf`	HiPAR-DSP 16, a scalable highly parallel DSP core for system on a chip video- and image processing applications. ICASSP Helge Kloos, Jens Peter Wittenburg, Willm Hinrichs, Hanno Lieske, Lars Friebe, C. Klar, Peter Pirsch
2002	C	`conf`	Highly efficient simulation environment for HDTV video decoder in VLSI design. VCIP Xun Mao, Wei Wang, Huimin Gong, Yan L. He, Jian Lou, Lu Yu, Qingdong Yao, Peter Pirsch
2002	J	`jnl`	Multicore system-on-chip architecture for MPEG-4 streaming video. IEEE Trans. Circuits Syst. Video Technol. Mladen Berekovic, Hans-Joachim Stolberg, Peter Pirsch
2002	—	`conf`	Processor Architectures for Multimedia Applications. Embedded Processor Design Challenges Peter Pirsch, Achim Freimann, C. Klar, Jens Peter Wittenburg
2001	Misc	`conf`	A programmable co-porcessor for MPEG-4 video. ICASSP Mladen Berekovic, Hans-Joachim Stolberg, Peter Pirsch, Holger Runge
2001	J	`jnl`	Architecture Concepts for Multimedia Signal Processing. J. VLSI Signal Process. Peter Pirsch, Carsten Reuter, Jens Peter Wittenburg, Mark Bernd Kulaczewski, Hans-Joachim Stolberg
2001	—	`conf`	CHIPDESIGN - A Novel Project-oriented Microelectronics Course. MSE Mark Bernd Kulaczewski, Stefan Zimmerman, Erich Barke, Peter Pirsch
2001	A	`conf`	Implementing The MPEG-4 Advanced Simple Profile For Streaming Video Applications. ICME Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch, Holger Runge
2000	J	`jnl`	A 1.3-GOPS parallel DSP for high-performance image-processing applications. IEEE J. Solid State Circuits Willm Hinrichs, Jens Peter Wittenburg, Hanno Lieske, Helge Kloos, Martin Ohmacht, Peter Pirsch
2000	—	`conf`	Architecture of an Image Rendering Co-Processor for MPEG-4 Systems. ASAP Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo
2000	C	`conf`	Co-processor architecture for MPEG-4 main profile visual compositing. ISCAS Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo
2000	—	`conf`	Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit. DFT Klaus Herrmann, Sören Moch, Jörg Hilgenstock, Peter Pirsch
2000	—	`ed.`	Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings PATMOS Dimitrios Soudris, Peter Pirsch, Erich Barke
2000	J	`jnl`	Rapid Prototyping von Videosignalverarbeitungsverfahren (Rapid Prototyping of Video Processing Schemes). Informationstechnik Tech. Inform. Carsten Reuter, Holger Kropp, Peter Pirsch
2000	C	`conf`	The M-PIRE MPEG-4 codec DSP and its macroblock engine. ISCAS Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch, Holger Runge, Henning Möller, Johannes Kneip
1999	B	`conf`	An FPGA-based Prototyping System for Real-Time Verification of Video Processing Schemes. FPL Holger Kropp, Carsten Reuter, Matthias Wiege, Tien-Toan Do, Peter Pirsch
1999	—	`conf`	Architecture of a hardware module for MPEG-4 shape decoding. ISCAS (1) Mladen Berekovic, K. Jacob, Peter Pirsch
1999	—	`conf`	Cellular Multiprocessor Arrays with Adaptive Resource Utilization. ACPC Hans-Joachim Stolberg, Martin Ohmacht, Peter Pirsch
1999	J	`jnl`	Guest Editors' Introduction. J. VLSI Signal Process. Mohammad Ibrahim, Peter Pirsch, Johan McCanny
1999	—	`conf`	Hardware Realisierung einer JAVA Virtual Machine für High Performance Multimedia-Anwendungen. ARCS Helge Kloos, Mladen Berekovic, Peter Pirsch
1999	J	`jnl`	Hardware Realization of a Java Virtual Machine for High Performance Multimedia Applications. J. VLSI Signal Process. Mladen Berekovic, Helge Kloos, Peter Pirsch
1999	—	`conf`	HiPAR-DSP: Ein 1.3 GOPS Multimedia Signalprozessor. ARCS Jens Peter Wittenburg, Willm Hinrichs, Martin Ohmacht, Hanno Lieske, Helge Kloos, Peter Pirsch
1999	J	`jnl`	Instruction Set Extensions for MPEG-4 Video. J. VLSI Signal Process. Mladen Berekovic, Hans-Joachim Stolberg, Mark Bernd Kulaczewski, Peter Pirsch, Henning Möller, Holger Runge, Johannes Kneip, Benno Stabernack
1999	—	`conf`	Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM. Great Lakes Symposium on VLSI Jörg Hilgenstock, Klaus Herrmann, Peter Pirsch
1998	B	`conf`	A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs. FPL Tien-Toan Do, Holger Kropp, Carsten Reuter, Peter Pirsch
1998	A*	`conf`	A Video Signal Processor for MIMD Multiprocessing. DAC Jörg Hilgenstock, Klaus Herrmann, Jan Otterstedt, Dirk Niggemeyer, Peter Pirsch
1998	Misc	`conf`	A flexible processor architecture for MPEG-4 image compositing. ICASSP Mladen Berekovic, Rainer Frase, Peter Pirsch
1998	J	`jnl`	An Algorithm-Hardware-System Approach to VLIW Multimedia Processors. J. VLSI Signal Process. Mladen Berekovic, Peter Pirsch, Johannes Kneip
1998	C	`conf`	An Array Processor Architecture with Parallel Data Cache for Image Rendering and Compositing. Computer Graphics International Mladen Berekovic, Peter Pirsch
1998	—	`conf`	Architecture of a coprocessor module for image compositing. ICECS Mladen Berekovic, Peter Pirsch
1998	—	`book`	Architectures for digital signal processing. Peter Pirsch
1998	A*	`conf`	Realization of a Programmable Parallel DSP for High Performance Image Processing Applications. DAC Jens Peter Wittenburg, Willm Hinrichs, Johannes Kneip, Martin Ohmacht, Mladen Berekovic, Hanno Lieske, Helge Kloos, Peter Pirsch
1998	C	`conf`	The Video and Image Processing Emulation System VIPES. International Workshop on Rapid System Prototyping Holger Kropp, Carsten Reuter, Peter Pirsch
1998	—	`conf`	VLSI architectures for multimedia. ICECS Peter Pirsch, Hans-Joachim Stolberg
1998	J	`jnl`	VLSI implementations of image and video multimedia processing systems. IEEE Trans. Circuits Syst. Video Technol. Peter Pirsch, Hans-Joachim Stolberg
1997	J	`jnl`	An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor. J. VLSI Signal Process. Johannes Kneip, Mladen Berekovic, Jens Peter Wittenburg, Willm Hinrichs, Peter Pirsch
1997	C	`conf`	An algorithm-hardware-system approach to VLIW multimedia processors. MMSP Johannes Kneip, Mladen Berekovic, Peter Pirsch
1997	—	`conf`	Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary Algorithms. ASAP Carsten Reuter, Markus Schwiegershausen, Peter Pirsch
1997	J	`jnl`	Implementation of media processors. IEEE Signal Process. Mag. Peter Pirsch, Hans-Joachim Stolberg, Yan-Kuang Chen, Sun-Yuan Kung
1997	B	`conf`	Implementation of pipelined multipliers on Xilinx FPGAs. FPL Tien-Toan Do, Holger Kropp, Markus Schwiegershausen, Peter Pirsch
1996	Misc	`conf`	A CAD tool for the optimization of video signal processor architectures. ICASSP Holger Kropp, Markus Schwiegershausen, Peter Pirsch
1996	—	`conf`	A system level HW/SW partitioning and optimization tool. EURO-DAC Markus Schwiegershausen, Holger Kropp, Peter Pirsch
1996	—	`book`	Architekturen der digitalen Signalverarbeitung. Peter Pirsch
1996	—	`conf`	Design of a development system for multimedia applications based on a single chip multiprocessor array. ICECS Klaus Herrmann, Klaus Gaedke, Jörg Hilgenstock, Peter Pirsch
1995	—	`conf`	A formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemes. EURO-DAC Markus Schwiegershausen, Peter Pirsch
1995	—	`conf`	A system level design methodology for the optimization of heterogeneous multiprocessors. ISSS Markus Schwiegershausen, Peter Pirsch
1995	J	`jnl`	Architecture and C++-programming environment of a highly parallel image signal processor. Microprocess. Microprogramming Johannes Kneip, Martin Ohmacht, Karsten Rönner, Peter Pirsch
1995	C	`conf`	Architecture and Memory Requirements for Stand-Alone and Hierarchical MPEG2 HDTV-Decoders with Synchronous DRAMs. ISCAS Marco Winzker, Peter Pirsch, Jochen Reimers
1995	C	`conf`	Parallelization Resources of Image Processing Algorithms and Their Mapping on a Programmable Parallel Videosignal Processor. ISCAS Peter Pirsch, Johannes Kneip, Karsten Rönner
1995	J	`jnl`	The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques. J. VLSI Signal Process. Mirjam Schönfeld, Jens Franzen, Markus Schwiegershausen, Peter Pirsch, Uwe Vehlies, Andreas Münzner
1995	J	`jnl`	VLSI architectures for video compression-a survey. Proc. IEEE Peter Pirsch, Nicolas Demassieux, Winfred Gehrke
1994	—	`conf`	A data path array with shared memory as core of a high performance DSP. ASAP Johannes Kneip, Karsten Rönner, Peter Pirsch
1994	—	`conf`	A hierarchical multiprocessor architecture based on heterogeneous processors for video coding applications. ICASSP (2) Winfried Gehrke, Richard Hoffer, Peter Pirsch
1993	C	`conf`	A Fault-tolerant DCT-Architecture Based on Distributed Arithmetic. ISCAS Klaus Gaedke, Jens Franzen, Peter Pirsch
1993	C	`conf`	A Hierarchical Multiprocessor Achitecture for Video Coding Applications. ISCAS Peter Pirsch, Winfried Gehrke, Richard Hoffer
1993	J	`jnl`	A VLSI based MIMD architecture of a multiprocessor system for real-time video processing applications. J. VLSI Signal Process. Klaus Gaedke, Hartwig Jeschke, Peter Pirsch
1993	J	`jnl`	A defect-tolerant systolic array implementation for real time image processing. J. VLSI Signal Process. V. Hecht, Karsten Rönner, Peter Pirsch
1993	J	`jnl`	Coding Algorithms and VLSI Implementations for Digital TV and HDTV Satellite Broadcasting. Eur. Trans. Telecommun. Hans Georg Musmann, Peter Pirsch
1993	—	`conf`	Compact hardware realization for Hough based extraction of line segments in image sequences for vehicle guidance. ICASSP (1) Jörg Schönfeld, Peter Pirsch
1993	—	`conf`	Single board image processing unit for vehicle guidance. VLSI Jörg Schönfeld, Peter Pirsch
1993	J	`jnl`	VLSI chip set for 2D HDTV subband filtering with on-chip line memories. IEEE J. Solid State Circuits Marco Winzker, Klaus Grüger, Winfried Gehrke, Peter Pirsch
1992	J	`jnl`	Multiprocessor performance for real-time processing of video coding applications. IEEE Trans. Circuits Syst. Video Technol. Hartwig Jeschke, Klaus Gaedke, Peter Pirsch
1991	—	`conf`	A defect tolerant systolic array implementation for real time image processing. ASAP V. Hecht, Karsten Rönner, Peter Pirsch
1991	—	`conf`	Synthesis of Intermediate Memories needed for the Data Supply to Processor Arrays. VLSI Mirjam Schönfeld, Markus Schwiegershausen, Peter Pirsch
1991	—	`conf`	Synthesis of intermediate memories for the data supply to processor arrays. Algorithms and Parallel VLSI Architectures Mirjam Schönfeld, Markus Schwiegershausen, Peter Pirsch
1990	C	`conf`	VLSI components for a 560-Mbit/s HDTV codec. VCIP Klaus Grüger, Peter Pirsch, Josef Kraus, Jochen Reimers
1989	Misc	`conf`	VLSI architectures for block matching algorithms. ICASSP Thomas Komarek, Peter Pirsch
1985	J	`jnl`	Advances in picture coding. Proc. IEEE Hans Georg Musmann, Peter Pirsch, Hans-Joachim Grallert
1985	J	`jnl`	Design of a DPCM codec for VLSI realization in CMOS technology. Proc. IEEE Peter Pirsch
1984	—	`conf`	Circuit Technique for VLSI Design of a Video Codec. ICC (1) Paul Drews, Peter Pirsch, K. Schaper
1983	J	`jnl`	Transmission of gray level images by multilevel dither techniques. Comput. Graph. Peter Pirsch, Arun N. Netravali
1982	J	`jnl`	Stability Conditions for DPCM Coders. IEEE Trans. Commun. Peter Pirsch
1981	J	`jnl`	Design of DPCM Quantizers for Video Signals Using Subjective Tests. IEEE Trans. Commun. Peter Pirsch