Peter Malík

24 papers C 12Journal 8Unranked 3
YearRankTypeTitle / Venue / Authors
2025 C conf
AI classifier of defects in Artworks captured by active infrared thermography.
FedCSIS
Peter Malík, Martin Orlej, Branislav Fajcák, Massimo Rippa
2024 J jnl
From Anomaly Detection to Defect Classification.
Sensors
Jaromír Klarák, Robert Andok, Peter Malík, Ivan Kuric, Mário Ritomský, Ivana Klacková, Hung-Yin Tsai
2023 J jnl
Crop Mapping without Labels: Investigating Temporal and Spatial Transferability of Crop Classification Models Using a 5-Year Sentinel-2 Series and Machine Learning.
Remote. Sens.
Tomas Rusnak, Tomás Kasanický, Peter Malík, Ján Mojzis, Ján Zelenka, Michal Svicek, Dominik Abrahám, Andrej Halabuk
2021 C conf
StarCraft strategy classification of a large human versus human game replay dataset.
FedCSIS
Stefan Kristofík, Matús Kasás, Peter Malík
2020 — ch.
AI Architectures for Very Smart Sensors.
Convergence of Artificial Intelligence and the Internet of Things
Peter Malík, Stefan Kristofík
2020 C conf
Instance Segmentation Model Created from Three Semantic Segmentations of Mask, Boundary and Centroid Pixels Verified on GlaS Dataset.
FedCSIS
Peter Malík, Kristína Knapová, Stefan Kristofík
2020 C conf
StarCraft agent strategic training on a large human versus human game replay dataset.
FedCSIS
Stefan Kristofík, Matús Kasás, Stefan Neupauer, Peter Malík
2019 J jnl
Machine Learning and Deep Learning frameworks and libraries for large-scale data mining: a survey.
Artif. Intell. Rev.
Giang Nguyen, Stefan Dlugolinský, Martin Bobák, Viet D. Tran, Álvaro López García, Ignacio Heredia, Peter Malík, Ladislav Hluchý
2019 J jnl
Universal framework for remote firmware updates of low-power devices.
Comput. Commun.
Ondrej Kachman, Marcel Baláz, Peter Malík
2018 J jnl
Enhancement of fault collection for embedded RAM redundancy analysis considering intersection and orphan faults.
Integr.
Stefan Kristofík, Peter Malík
2018 J jnl
Hardware redundancy architecture based on reconfigurable logic blocks with persistent high reliability improvement.
Microelectron. Reliab.
Stefan Kristofík, Marcel Baláz, Peter Malík
2016 J jnl
Dedicated Hardware for Complex Mathematical Operations.
Comput. Informatics
Peter Malík
2016 — conf
Natural logarithm and division floating-point high throughput co-processor implemented in FPGA.
NORCAS
Peter Malík
2015 — conf
High Throughput Floating Point Exponential Function Implemented in FPGA.
ISVLSI
Peter Malík
2015 C conf
High Throughput Floating-Point Dividers Implemented in FPGA.
DDECS
Peter Malík
2014 C conf
Dedicated hardware architecture for object tracking preprocessing implemented in FPGA.
DDECS
Peter Malík
2011 J jnl
Highly scalable IP core to accelerate the forward/backward modified discrete cosine transform in MP3 implemented to FPGA and low-power ASIC.
IET Circuits Devices Syst.
Peter Malík
2009 C conf
MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio.
DDECS
Peter Malík, Michal Ufnal, Arkadiusz W. Luczyk, Marcel Baláz, Witold A. Pleskacz
2008 C conf
Various MDCT implementations in 0.35µm CMOS.
DDECS
Peter Malík, Marcel Baláz, Martin Simlastík, Arkadiusz W. Luczyk, Witold A. Pleskacz
2007 — conf
A Generic IP Core of the Identical Forward and Inverse 12/36-Point MDCT Architecture and an Architectural Model Simulation Toolbox.
ICECS
Peter Malík
2007 C conf
An Improved MDCT IP Core Generator with Architectural Model Simulation.
DDECS
Peter Malík, Marcel Baláz, Tomás Pikula, Martin Simlastík
2007 C conf
Clockless Implementation of LEON2 for Low-Power Applications.
DDECS
Martin Simlastík, Viera Stopjaková, Libor Majer, Peter Malík
2006 C conf
FPGA Implementation of a Fast MDCT Algorithm.
DDECS
Martin Simlastík, Peter Malík, Tomás Pikula, Marcel Baláz
2006 C conf
MDCT IP Core Generator with Architectural Model Simulation.
VLSI-SoC
Peter Malík, Marcel Baláz, Tomás Pikula, Martin Simlastík