Peter M. Maurer

53 papers A* 4A 10Misc 3Journal 18Unranked 18

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Discrete random variates with finite support using differential search trees. Simul. Peter M. Maurer
2023	—	`conf`	DGL Version 2 - Random Testing in the Mobile Computing Era. SDSC Peter M. Maurer
2022	—	`conf`	Generating Random XML Files Using DGL. CSCI Peter M. Maurer, John Carbone
2022	—	`conf`	Teaching Induction and Deductive Reasoning. CSCI Peter M. Maurer
2021	—	`conf`	Computer Science Theory from a Practical Point of View. CSCI Peter M. Maurer
2021	—	`conf`	Massive Generation of Data with Random Variates. ANNSIM Peter M. Maurer
2019	—	`conf`	A nominal/inertial delay metamorphic differential simulator. SummerSim Peter M. Maurer
2017	—	`conf`	Finite random variates using differential search trees. SummerSim Peter M. Maurer
2016	—	`conf`	Time-parallel multi-delay logic simulation. SpringSim (TMS-DEVS) Peter M. Maurer
2015	—	`conf`	A second look at oblivious simulation. SummerSim Peter M. Maurer
2015	—	`conf`	Levelized compiled code multi-delay logic simulation. SpringSim (TMS-DEVS) Peter M. Maurer
2014	A	`conf`	A universal symmetry detection algorithm. DATE Peter M. Maurer
2013	—	`conf`	Metamorphic differential simulation using the multi-delay timing model. SpringSim (TMS-DEVS) Peter M. Maurer
2012	—	`conf`	Extending symmetric variable-pair transitivities using state-space transformations. ACM Great Lakes Symposium on VLSI Peter M. Maurer
2011	J	`jnl`	Conjugate symmetry. Formal Methods Syst. Des. Peter M. Maurer
2006	A	`conf`	Using conjugate symmetries to enhance gate-level simulations. DATE Peter M. Maurer
2005	J	`jnl`	Converting command-line applications into binary components. Softw. Pract. Exp. Peter M. Maurer
2005	—	`conf`	How to Make Program Assessment Work for You. FECS William B. Poucher, Peter M. Maurer
2004	J	`jnl`	Metamorphic Programming: Unconventional High Performance. Computer Peter M. Maurer
2003	J	`jnl`	Efficient event-driven simulation by exploiting the output observability of gate clusters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peter M. Maurer
2003	—	`conf`	Random Characterization of Design Automation Algorithms. ISVLSI Sandeep K. Kondapuram, Peter M. Maurer
2001	A	`conf`	Identifying an appropriate view of software components for undergraduate education. SIGCSE Allen S. Parrish, Joe Hollingsworth, Peter M. Maurer, Benjamin Shults, Bruce W. Weide
2000	J	`jnl`	Components: What If They Gave a Revolution and Nobody Came? Computer Peter M. Maurer
2000	A	`conf`	Event Driven Simulation Without Loops or Conditionals. ICCAD Peter M. Maurer
2000	A	`conf`	Logic Simulation Using Networks of State Machines. DATE Peter M. Maurer
2000	Misc	`conf`	State-Machine Based Logic Simulation Using Three Logic Values. VLSI Design Peter M. Maurer, William J. Schilp
1999	Misc	`conf`	Efficient Simulation for Hierarchical and Partitioned Circuits. VLSI Design Peter M. Maurer
1999	A	`conf`	Software Bit-Slicing: A Technique for Improving Simulation Performance. DATE Peter M. Maurer, William J. Schilp
1997	J	`jnl`	The inversion algorithm for digital simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peter M. Maurer
1996	J	`jnl`	Bit-parallel multidelay simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yun Sik Lee, Peter M. Maurer
1996	Misc	`conf`	Is Compiled Simulation Really Faster than Interpreted Simulation? VLSI Design Peter M. Maurer
1996	A	`conf`	Unit delay simulation with the inversion algorithm. ICCAD William J. Schilp, Peter M. Maurer
1994	J	`jnl`	Gateways: a technique for adding event-driven behavior to compiled simulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peter M. Maurer, Yun Sik Lee
1994	A	`conf`	The Inversion Algorithm for digital simulation. ICCAD Peter M. Maurer
1993	A	`conf`	Parallel multi-delay simulation. ICCAD Yun Sik Lee, Peter M. Maurer
1993	J	`jnl`	The shadow algorithm: a scheduling technique for both compiled and interpreted simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peter M. Maurer
1992	J	`jnl`	The Design and Implementation of a Grammar-based Data Generator. Softw. Pract. Exp. Peter M. Maurer
1992	A*	`conf`	Two New Techniques for Compiled Multi-Delay Logic Simulation. DAC Yun Sik Lee, Peter M. Maurer
1992	J	`jnl`	Two new techniques for unit-delay compiled simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peter M. Maurer
1991	J	`jnl`	Scheduling blocks of hierarchical compiled simulation of combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peter M. Maurer
1990	J	`jnl`	Dynamic Functional Testing for VLSI Circuits. IEEE Des. Test Comput. Peter M. Maurer
1990	J	`jnl`	Generating Test Data with Enhanced Context-Free Grammars. IEEE Softw. Peter M. Maurer
1990	A*	`conf`	LECSIM: A Levelized Event Driven Compiled Logic Simulation. DAC Zhicheng Wang, Peter M. Maurer
1990	A	`conf`	Optimization of the Parallel Technique for Compiled Unit-Delay Simulation. ICCAD Peter M. Maurer
1990	A*	`conf`	Techniques for Unit-Delay Compiled Simulation. DAC Peter M. Maurer, Zhicheng Wang
1990	—	`conf`	The FHDL PLA tools. ACM Southeast Regional Conference Peter M. Maurer, Craig D. Morency
1990	—	`conf`	The FHDL ROM tools. ACM Southeast Regional Conference Peter M. Maurer, Craig D. Morency
1990	—	`conf`	The FHDL macro processor. ACM Southeast Regional Conference Peter M. Maurer
1989	A*	`conf`	Scheduling High-Level Blocks for Functional Simulation. DAC Zhicheng Wang, Peter M. Maurer
1988	J	`jnl`	A logic-to-logic comparator for VLSI layout verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peter M. Maurer, Alexander D. Schapira
1988	J	`jnl`	Design verification of the WE 32106 math accelerator unit. IEEE Des. Test Peter M. Maurer
1988	—	`conf`	Mapping the Data Flow Model of Computation into an Enhanced Von Neumann Processor. ICPP (1) Peter M. Maurer
1983	J	`jnl`	The Use of Combinators in Translating A Purely Functional Language to Low-Level Data-Flow Graphs. Comput. Lang. Peter M. Maurer, Arthur E. Oldehoeft