Peter M. Kelly

28 papers B 8C 1Misc 1Journal 6Unranked 12

Year	Rank	Type	Title / Venue / Authors
2011	B	`conf`	Evaluating the training dynamics of a CMOS based synapse. IJCNN Arfan Ghani, Liam McDaid, Ammar Belatreche, Peter M. Kelly, Steve Hall, Thomas Dowrick, Shou Huang, John Marsland, Andy W. Smith
2011	J	`jnl`	On Two-Layer Brain-Inspired Hierarchical Topologies - A Rent's Rule Approach -. Trans. High Perform. Embed. Archit. Compil. Valeriu Beiu, Basheer A. M. Madappuram, Peter M. Kelly, Liam McDaid
2009	J	`jnl`	Lambda calculus as a workflow model. Concurr. Comput. Pract. Exp. Peter M. Kelly, Paul D. Coddington, Andrew L. Wendelborn
2009	—	`conf`	On Two-Layer Hierarchical Networks How Does the Brain Do This? NanoNet Valeriu Beiu, Basheer A. M. Madappuram, Peter M. Kelly, Liam McDaid
2009	—	`conf`	Reduced Interconnects in Neural Networks Using a Time Multiplexed Architecture Based on Quantum Devices. NanoNet Peter M. Kelly, Fergal Tuffy, Valeriu Beiu, Liam McDaid
2008	J	`jnl`	A Solid-State Neuron for Spiking Neural Network Implementation. Eng. Lett. Yajie Chen, Steve Hall, Liam McDaid, Octavian Buiu, Peter M. Kelly
2008	B	`conf`	A programmable facilitating synapse device. IJCNN Yajie Chen, Liam McDaid, Steve Hall, Peter M. Kelly
2008	—	`conf`	A time multiplexed architecture for neural networks using quantum devices. ICECS Peter M. Kelly, Liam McDaid, Fergal Tuffy, T. Martin McGinnity
2008	—	`conf`	Lambda Calculus as a Workflow Model. GPC Workshops Peter M. Kelly, Paul D. Coddington, Andrew L. Wendelborn
2008	—	`conf`	On brain-inspired connectivity and hybrid network topologies. NANOARCH Basheer A. M. Madappuram, Valeriu Beiu, Peter M. Kelly, Liam McDaid
2007	B	`conf`	A Biologically Plausible Neuron Circuit. IJCNN Thomas Dowrick, Steve Hall, Liam McDaid, Octavian Buiu, Peter M. Kelly
2007	C	`conf`	A Distributed Virtual Machine for Parallel Graph Reduction. PDCAT Peter M. Kelly, Paul D. Coddington, Andrew L. Wendelborn
2007	—	`conf`	Analog Spiking Neuron with Charge-Coupled Synapses. World Congress on Engineering Yajie Chen, Steve Hall, Liam McDaid, Octavian Buiu, Peter M. Kelly
2007	J	`jnl`	Inter-neuron communication strategies for spiking neural networks. Neurocomputing Fergal Tuffy, L. J. McDaid, Vunfu Wong Kwan, John Alderman, T. Martin McGinnity, Jose A. Santos, Peter M. Kelly, Heather M. Sayers
2006	—	`conf`	A Silicon Synapse Based on a Charge Transfer Device for Spiking Neural Network Application. ISNN (2) Yajie Chen, Steve Hall, Liam McDaid, Octavian Buiu, Peter M. Kelly
2006	—	`conf`	A Time Multiplexing Architecture for Inter-neuron Communications. ICANN (1) Fergal Tuffy, Liam McDaid, T. Martin McGinnity, Jose Santos, Peter M. Kelly, Vunfu Wong Kwan, John Alderman
2006	—	`conf`	A simplified approach to web service development. ACSW Peter M. Kelly, Paul D. Coddington, Andrew L. Wendelborn
2006	B	`conf`	Compilation of XSLT into Dataflow Graphs for Web Service Composition. CCGRID Peter M. Kelly, Paul D. Coddington, Andrew L. Wendelborn
2006	B	`conf`	Inter-Neuron Communications for Large-Scale Neural Networks using Capacitive Coupling. IJCNN Fergal Tuffy, Liam McDaid, Vunfu Wong Kwan, John Alderman, T. Martin McGinnity, Peter M. Kelly, Jose A. Santos
2006	B	`conf`	On the Design of a Low Power Compact Spiking Neuron Cell Based on Charge-Coupled Synapses. IJCNN Yajie Chen, Steve Hall, Liam McDaid, Octavian Buiu, Peter M. Kelly
2005	Misc	`conf`	A Quaternary CLB Design Using Quantum Device Technology on Silicon for FPGA Neural Network Architectures. IWANN Peter M. Kelly, T. Martin McGinnity, Liam P. Maguire, L. J. McDaid
2005	B	`conf`	Distributed, Parallel Web Service Orchestration Using XSLT. e-Science Peter M. Kelly, Paul D. Coddington, Andrew L. Wendelborn
2005	—	`conf`	Reducing Interconnection Resource Overhead in Nano-scale FPGAs through MVL Signal Systems. ASAP Peter M. Kelly, T. Martin McGinnity, Liam P. Maguire
2004	B	`conf`	Architectural requirements for threshold logic gates based on resonant tunneling devices. IJCNN Peter M. Kelly, T. M. McGinnity, Liam P. Maguire
2003	—	`conf`	A Binary Multiplier Using RTD Based Threshold Logic Gates. IWANN (2) Peter M. Kelly, C. J. Thompson, T. Martin McGinnity, Liam P. Maguire
2003	J	`jnl`	Re-Programmable MVL Circuits and Architecture to Enable Evolvable MVL Hardware. J. Multiple Valued Log. Soft Comput. Peter M. Kelly, T. Martin McGinnity, Liam P. Maguire
2002	—	`conf`	Investigation of a programmable threshold logic gate array. ICECS Peter M. Kelly, C. J. Thompson, T. M. McGinnity, Liam P. Maguire
1977	J	`jnl`	Implementing Spread Spectrum Technology in the Land Mobile Radio Services. IEEE Trans. Commun. Robert P. Eckert, Peter M. Kelly