Peter Hazucha

16 papers A 1C 1Journal 10Unranked 4
YearRankTypeTitle / Venue / Authors
2009 J jnl
A Delay-Locked Loop Synchronization Scheme for High-Frequency Multiphase Hysteretic DC-DC Converters.
IEEE J. Solid State Circuits
Pengfei Li, Lin Xue, Peter Hazucha, Tanay Karnik, Rizwan Bashirullah
2008 J jnl
A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction.
IEEE J. Solid State Circuits
Jianping Xu, Peter Hazucha, Zuoguo Wu, Paolo A. Aseron, Mingwei Huang, Fabrice Paillet, Gerhard Schrom, James W. Tschanz, Vivek De, Tanay Karnik, Greg Taylor
2007 J jnl
High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters.
IEEE J. Solid State Circuits
Peter Hazucha, Sung Tae Moon, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner, Saravanan Rajapandian, Tanay Karnik
2007 — conf
Low Voltage Buffered Bandgap Reference.
ISQED
Peter Hazucha, Fabrice Paillet, Sung Tae Moon, David J. Rennie, Gerhard Schrom, Donald S. Gardner, Kenneth Ikeda, Gell Gellman, Tanay Karnik
2007 — conf
On-Die Supply-Resonance Suppression Using Band-Limited Active Damping.
ISSCC
Jianping Xu, Peter Hazucha, Mingwei Huang, Paolo A. Aseron, Fabrice Paillet, Gerhard Schrom, James W. Tschanz, Cangsang Zhao, Vivek De, Tanay Karnik, Greg Taylor
2006 — conf
A Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC Converters.
ISSCC
Peter Hazucha, Sung Tae Moon, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner, Saravanan Rajapandian, Tanay Karnik
2006 C conf
High-frequency DC-DC conversion : fact or fiction.
ISCAS
Tanay Karnik, Peter Hazucha, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner
2006 J jnl
High-voltage power delivery through charge recycling.
IEEE J. Solid State Circuits
Saravanan Rajapandian, Kenneth L. Shepard, Peter Hazucha, Tanay Karnik
2005 J jnl
A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package.
IEEE J. Solid State Circuits
Peter Hazucha, Gerhard Schrom, Jaehong Hahn, Bradley A. Bloechel, Paul Hack, Gregory E. Dermer, Siva G. Narendra, Donald S. Gardner, Tanay Karnik, Vivek De, Shekhar Borkar
2005 J jnl
Area-efficient linear regulator with ultra-fast load regulation.
IEEE J. Solid State Circuits
Peter Hazucha, Tanay Karnik, Bradley A. Bloechel, Colleen Parsons, David Finan, Shekhar Borkar
2004 J jnl
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes.
IEEE Trans. Dependable Secur. Comput.
Tanay Karnik, Peter Hazucha, Jagdish Patel
2004 A conf
Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation.
ISLPED
Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva G. Narendra, Tanay Karnik, Vivek De
2004 J jnl
Measurements and analysis of SER-tolerant latch in a 90-nm dual-V
IEEE J. Solid State Circuits
Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar
2003 — conf
Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process.
CICC
Peter Hazucha, Tanay Kamik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Greg Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar
2000 J jnl
Cosmic-ray soft error rate characterization of a standard 0.6-μm CMOS process.
IEEE J. Solid State Circuits
Peter Hazucha, Christer Svensson, Stephen A. Wender
2000 J jnl
Optimized test circuits for SER characterization of a manufacturing process.
IEEE J. Solid State Circuits
Peter Hazucha, Christer Svensson