Peter Figuli

15 papers A* 1B 1C 1Journal 2Unranked 10
YearRankTypeTitle / Venue / Authors
2022 A* conf
AI accelerator on IBM telum processor: industrial product.
ISCA
Cédric Lichtenau, Alper Buyuktosunoglu, Ramon Bertran, Peter Figuli, Christian Jacobi, Nikolaos Papandreou, Haris Pozidis, Anthony Saporito, Andrew Sica, Elpida Tzortzatos
2017 — conf
A reconfigurable high-speed spiral FIR filter architecture.
TSP
Shalina Percy Delicia Figuli, Peter Figuli, Jürgen Becker
2017 — conf
Parameter Sensitivity in Virtual FPGA Architectures.
ARC
Peter Figuli, Weiqiao Ding, Shalina Percy Delicia Figuli, Kostas Siozios, Dimitrios Soudris, Jürgen Becker
2016 — conf
A variable FPGA based generic QAM transmitter with scalable mixed time and frequency domain signal processing.
TSP
Shalina Percy Delicia Figuli, Alberto Sonnino, Peter Figuli, Jürgen Becker
2016 J jnl
High-Speed Medical Imaging in 3D Ultrasound Computer Tomography.
IEEE Trans. Parallel Distributed Syst.
Matthias Birk, Ernst Kretzek, Peter Figuli, Marc Weber, Jürgen Becker, Nicole V. Ruiter
2015 — conf
A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware.
ARC
Peter Figuli, Carsten Tradowsky, Jose Martinez, Harry Sidiropoulos, Kostas Siozios, Holger Stenschke, Dimitrios Soudris, Jürgen Becker
2015 — conf
A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models.
SAMOS
Efstathios Sotiriou-Xanthopoulos, Shalina Percy Delicia, Peter Figuli, Kostas Siozios, George Economakos, Jürgen Becker
2015 C conf
Parametric design space exploration for optimizing QAM based high-speed communication.
ICCC
Shalina Percy Delicia, George Ford, Peter Figuli, Jürgen Becker
2015 — conf
TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools.
ARC
Kostas Siozios, Peter Figuli, Harry Sidiropoulos, Carsten Tradowsky, Dionysios Diamantopoulos, Konstantinos Maragos, Shalina Percy Delicia, Dimitrios Soudris, Jürgen Becker
2013 B conf
A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization.
FPL
Harry Sidiropoulos, Peter Figuli, Kostas Siozios, Dimitrios Soudris, Jürgen Becker
2013 J jnl
JITPR: A framework for supporting fast application's implementation onto FPGAs.
ACM Trans. Reconfigurable Technol. Syst.
Harry Sidiropoulos, Kostas Siozios, Peter Figuli, Dimitrios Soudris, Michael Hübner, Jürgen Becker
2013 — conf
ViSA: A highly efficient slot architecture enabling multi-objective ASIP cores.
ISSoC
Peter Figuli, Carsten Tradowsky, Nadine Gaertner, Jürgen Becker
2012 — conf
On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation.
IPDPS Workshops
Harry Sidiropoulos, Kostas Siozios, Peter Figuli, Dimitrios Soudris, Michael Hübner
2011 — conf
A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture.
IPDPS Workshops
Michael Hübner, Peter Figuli, Romuald Girardey, Dimitrios Soudris, Kostas Siozios, Jürgen Becker
2011 — conf
A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime Core Fusion.
AHS
Peter Figuli, Michael Hübner, Romuald Girardey, Falco Bapp, Thomas Bruckschlögl, Florian Thoma, Jörg Henkel, Jürgen Becker