Peter Debacker

41 papers A* 1A 3B 1C 6Misc 1Journal 11Unranked 18

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis. CoRR Giuseppe Maria Sarda, Nimish Shah, Debjyoti Bhattacharjee, Peter Debacker, Marian Verhelst
2023	—	`conf`	A 2Mbit Digital in-Memory Computing Matrix-Vector Multiplier for DNN Inference supporting flexible bit precision and matrix size achieving 612 binary TOPS/W. ESSCIRC Mohit Gupta, Stefan Cosemans, Peter Debacker, Wim Dehaene
2023	J	`jnl`	DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge. IEEE J. Solid State Circuits Pouya Houshmand, Giuseppe Maria Sarda, Vikram Jain, Kodai Ueyoshi, Ioannis A. Papistas, Man Shi, Qilin Zheng, Debjyoti Bhattacharjee, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst
2023	—	`conf`	Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays. IMW Subhali Subhechha, Stefan Cosemans, Attilio Belmonte, Nouredine Rassoul, Shamin Houshmand Sharifi, Peter Debacker, Diederik Verkest, Romain Delhougne, Gouri Sankar Kar
2023	C	`conf`	Evaluating the Effects of FeFET Device Variability on Charge Sharing Based AiMC Accelerator. ISCAS Swatilekha Majumdar, Stefan Cosemans, Arindam Mallik, Peter Debacker, Francky Catthoor, Jan Van Houdt
2023	—	`conf`	Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis. IISWC Giuseppe Maria Sarda, Nimish Shah, Debjyoti Bhattacharjee, Peter Debacker, Marian Verhelst
2022	J	`jnl`	AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. Simei Yang, Debjyoti Bhattacharjee, Vinay B. Y. Kumar, Saikat Chatterjee, Sayandip De, Peter Debacker, Diederik Verkest, Arindam Mallik, Francky Catthoor
2022	J	`jnl`	Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization. IEEE Trans. Very Large Scale Integr. Syst. Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, Jaehyun Lee, Kangwei Xu, Vihar P. Georgiev, Kai Ni, Peter Debacker, Asen Asenov, Aida Todri-Sanial
2022	J	`jnl`	Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization. IEEE Trans. Very Large Scale Integr. Syst. Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, Jaehyun Lee, Kangwei Xu, Vihar P. Georgiev, Kai Ni, Peter Debacker, Asen Asenov, Aida Todri-Sanial
2022	—	`conf`	DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC. ISSCC Kodai Ueyoshi, Ioannis A. Papistas, Pouya Houshmand, Giuseppe Maria Sarda, Vikram Jain, Man Shi, Qilin Zheng, Juan Sebastian Piedrahita Giraldo, Peter Vrancx, Jonas Doevenspeck, Debjyoti Bhattacharjee, Stefan Cosemans, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst
2022	J	`jnl`	Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration. ACM Trans. Design Autom. Electr. Syst. Nathan Laubeuf, Jonas Doevenspeck, Ioannis A. Papistas, Michele Caselli, Stefan Cosemans, Peter Vrancx, Debjyoti Bhattacharjee, Arindam Mallik, Peter Debacker, Diederik Verkest, Francky Catthoor, Rudy Lauwereins
2022	Misc	`conf`	Learn to Learn on Chip: Hardware-aware Meta-learning for Quantized Few-shot Learning at the Edge. SEC Nitish Satya Murthy, Peter Vrancx, Nathan Laubeuf, Peter Debacker, Francky Catthoor, Marian Verhelst
2022	J	`jnl`	Memory Devices and A/D Interfaces: Design Tradeoffs in Mixed-Signal Accelerators for Machine Learning Applications. IEEE Trans. Circuits Syst. II Express Briefs Michele Caselli, Peter Debacker, Andrea Boni
2022	C	`conf`	Tiny ci-SAR A/D Converter for Deep Neural Networks in Analog in-Memory Computation. ISCAS Michele Caselli, Debjyoti Bhattacharjee, Arindam Mallik, Peter Debacker, Diederik Verkest
2022	C	`conf`	Write-Verify Scheme for IGZO DRAM in Analog in-Memory Computing. ISCAS Michele Caselli, Subhali Subhechha, Peter Debacker, Arindam Mallik, Diederik Verkest
2021	—	`conf`	A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm CICC Ioannis A. Papistas, Stefan Cosemans, Bram Rooseleer, Jonas Doevenspeck, Myung Hee Na, Arindam Mallik, Peter Debacker, Diederik Verkest
2021	—	`conf`	Charge Sharing and Charge Injection A/D Converters for Analog In-Memory Computing. NEWCAS Michele Caselli, Ioannis A. Papistas, Stefan Cosemans, Arindam Mallik, Peter Debacker, Diederik Verkest
2021	C	`conf`	Design-Technology Space Exploration for Energy Efficient AiMC-Based Inference Acceleration. ISCAS Debjyoti Bhattacharjee, Nathan Laubeuf, Stefan Cosemans, Ioannis A. Papistas, Arindam Mallik, Peter Debacker, Myung Hee Na, Diederik Verkest
2021	B	`conf`	Noise tolerant ternary weight deep neural networks for analog in-memory inference. IJCNN Jonas Doevenspeck, Peter Vrancx, Nathan Laubeuf, Arindam Mallik, Peter Debacker, Diederik Verkest, Rudy Lauwereins, Wim Dehaene
2019	C	`conf`	A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs. ICCD Timon Evenblij, Christian Tenllado, Manu Perumkunnil, Francky Catthoor, Sushil Sakhare, Peter Debacker, Gouri Sankar Kar, Arnaud Furnémont, Nicolas Bueno, José Ignacio Gómez Pérez
2019	—	`conf`	Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route. 3DIC Giuliano Sisto, Peter Debacker, Rongmei Chen, Geert Van der Plas, Richard Chou, Eric Beyne, Dragomir Milojevic
2019	J	`jnl`	FQ-Conv: Fully Quantized Convolution for Efficient and Accurate Inference. CoRR Bram-Ernst Verhoef, Nathan Laubeuf, Stefan Cosemans, Peter Debacker, Ioannis A. Papistas, Arindam Mallik, Diederik Verkest
2019	—	`conf`	Low Voltage Transient RESET Kinetic Modeling of OxRRAM for Neuromorphic Applications. IRPS Jonas Doevenspeck, Robin Degraeve, Andrea Fantini, Peter Debacker, Diederik Verkest, Rudy Lauwereins, Wim Dehaene
2019	—	`conf`	Sub-Word Parallel Precision-Scalable MAC Engines for Efficient Embedded DNN Inference. AICAS Linyan Mei, Mohit Dandekar, Dimitrios Rodopoulos, Jeremy Constantin, Peter Debacker, Rudy Lauwereins, Marian Verhelst
2017	A	`conf`	IR-drop aware Design & technology co-optimization for N5 node with different device and cell height options. ICCAD Luca Mattii, Dragomir Milojevic, Peter Debacker, Yasser Sherazi, Mladen Berekovic, Praveen Raghavan
2017	J	`jnl`	MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang
2017	C	`conf`	Patterning Aware Design Optimization of Selective Etching in N5 and Beyond. ICCD Yibo Lin, Peter Debacker, Darko Trivkovic, Ryoung-Han Kim, Praveen Raghavan, David Z. Pan
2017	A*	`conf`	Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes. DAC Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang
2016	—	`conf`	5nm: Has the time for a device change come? ISQED Praveen Raghavan, Marie Garcia Bardon, Peter Debacker, P. Schuddinck, Doyoung Jang, Rogier Baert, Diederik Verkest, Aaron Voon-Yew Thean
2016	—	`conf`	Capturing True Workload Dependency of BTI-induced Degradation in CPU Components. ACM Great Lakes Symposium on VLSI Dimitrios Stamoulis, Simone Corbetta, Dimitrios Rodopoulos, Pieter Weckx, Peter Debacker, Brett H. Meyer, Ben Kaczer, Praveen Raghavan, Dimitrios Soudris, Francky Catthoor, Zeljko Zilic
2016	J	`jnl`	Computation-skip Error Mitigation Scheme for Power Supply Voltage Scaling in Recursive Applications. J. Signal Process. Syst. Yanxiang Huang, Meng Li, Chunshu Li, Peter Debacker, Liesbet Van der Perre
2016	A	`conf`	How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node? ICCAD Bon Woong Ku, Peter Debacker, Dragomir Milojevic, Praveen Raghavan, Sung Kyu Lim
2016	A	`conf`	Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs. ISLPED Bon Woong Ku, Peter Debacker, Dragomir Milojevic, Praveen Raghavan, Diederik Verkest, Aaron Thean, Sung Kyu Lim
2015	—	`conf`	An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS. A-SSCC Meng Li, Jan-Willem Weijers, Veerle Derudder, Ilse Vos, Maxim Rykunov, Steven Dupont, Peter Debacker, Andy Dewilde, Yanxiang Huang, Liesbet Van der Perre, Wim Van Thillo
2014	—	`conf`	Computation-skip error resilient scheme for recursive CORDIC. SiPS Yanxiang Huang, Meng Li, Chunshu Li, Peter Debacker, Liesbet Van der Perre
2013	—	`conf`	A C-programmable baseband processor with inner modem implementations for LTE Cat-4/5/7 and Gbps 80MHz 4×4 802.11ac (invited). GlobalSIP Min Li, Amir Amin, Raf Appeltans, Andy Folens, Ubaid Ahmad, Hans Cappelle, Peter Debacker, Lieven Hollevoet, André Bourdoux, Praveen Raghavan, Antoine Dejonghe, Liesbet Van der Perre
2013	—	`conf`	A processor based multi-standard low-power LDPC engine for multi-Gbps wireless communication. GlobalSIP Meng Li, Frederik Naessens, Min Li, Peter Debacker, Claude Desset, Praveen Raghavan, Antoine Dejonghe, Liesbet Van der Perre
2013	—	`conf`	An area and energy efficient half-row-paralleled layer LDPC decoder for the 802.11AD standard. SiPS Meng Li, Frederik Naessens, Peter Debacker, Praveen Raghavan, Claude Desset, Min Li, Antoine Dejonghe, Liesbet Van der Perre
2012	J	`jnl`	Power Estimation at Different Abstraction Levels for Wireless Baseband Processors. J. Low Power Electron. Martin Palkovic, Peter Debacker, Prabhat Avasare, Steven Dupont, Tom Vander Aa
2009	—	`conf`	A novel positioning technique for the 2.4GHz ISM band. WPNC Huub Tubbax, Johan Wouters, Jan Olbrechts, Peter Debacker, Peter Spiessens, Frederic Stubbe, Johan Danneels
2005	—	`conf`	Dynamic Time-Slot Allocation for QoS Enabled Networks on Chip. ESTIMedia Théodore Marescaux, B. Bricke, Peter Debacker, Vincent Nollet, Henk Corporaal