Pervez M. Aziz

13 papers C 5Journal 4Unranked 4
YearRankTypeTitle / Venue / Authors
2014 — conf
2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS.
ISSCC
Hiroshi Kimura, Pervez M. Aziz, Tai Jing, Ashutosh Sinha, Ram Narayan, Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael C. Wang, Amaresh V. Malipatil, Shiva Kotagiri, Lijun Li, Christopher J. Abel, Freeman Zhong
2014 J jnl
A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS.
IEEE J. Solid State Circuits
Hiroshi Kimura, Pervez M. Aziz, Tai Jing, Ashutosh Sinha, Shiva Prasad Kotagiri, Ram Narayan, Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael C. Wang, Amaresh V. Malipatil, Lijun Li, Christopher J. Abel, Freeman Zhong
2014 C conf
Shift register multi-phase clock based downsampled floating tap DFE for serial links.
ISCAS
Pervez M. Aziz, Hiroshi Kimura, Amaresh V. Malipatil, Shiva Kotagiri, Gordon Chan, Hairong Gao
2013 C conf
Analysis of a class of decimated clock/data recovery architectures for serial links.
ISCAS
Pervez M. Aziz, Amaresh V. Malipatil
2012 C conf
A class of downsampled floating tap DFE architectures with application to serial links.
ISCAS
Pervez M. Aziz, Hiroshi Kimura, Amaresh V. Malipatil, Shiva Kotagiri
2011 J jnl
A 1.0625 ~ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS.
IEEE J. Solid State Circuits
Freeman Zhong, Shaolei Quan, Wing Liu, Pervez M. Aziz, Tai Jing, Jen Dong, Chintan Desai, Hairong Gao, Monica Garcia, Gary Hom, Tony Huynh, Hiroshi Kimura, Ruchi Kothari, Lijun Li, Cathy Liu, Scott Lowrie, Kathy Ling, Amaresh V. Malipatil, Ram Narayan, Tom Prokop, Chaitanya Palusa, Anil Rajashekara, Ashutosh Sinha, Charlie Zhong, Eric Zhang
2011 — conf
A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS.
ISSCC
Shaolei Quan, Freeman Zhong, Wing Liu, Pervez M. Aziz, Tai Jing, Jen Dong, Chintan Desai, Hairong Gao, Monica Garcia, Gary Hom, Tony Huynh, Hiroshi Kimura, Ruchi Kothari, Lijun Li, Cathy Liu, Scott Lowrie, Kathy Ling, Amaresh V. Malipatil, Ram Narayan, Tom Prokop, Chaitanya Palusa, Anil Rajashekara, Ashutosh Sinha, Charlie Zhong, Eric Zhang
2011 C conf
Adaptation algorithms for a class of continuous time analog equalizers with application to serial links.
ISCAS
Pervez M. Aziz, Amaresh V. Malipatil
2001 J jnl
Symbol rate timing recovery for higher order partial response channels.
IEEE J. Sel. Areas Commun.
Pervez M. Aziz, Srinivasan Surendran
1999 — conf
A rate 16/17 punctured MTR block code.
ICC
Pervez M. Aziz, Necip Sayiner, Viswanath Annampedu
1996 J jnl
An overview of sigma-delta converters.
IEEE Signal Process. Mag.
Pervez M. Aziz, Henrik V. Sorensen, Jan Van der Spiegel
1995 C conf
Performance of Complex Noise Transfer Functions in Bandpass and Multi Band Sigma Delta Systems.
ISCAS
Pervez M. Aziz, Henrik V. Sorensen, Jan Van der Spiegel
1994 — conf
Multi band sigma delta analog to digital conversion.
ICASSP (3)
Pervez M. Aziz, Henrik V. Sorensen, Jan Van der Spiegel