Per Stenström

216 papers A* 24A 30B 22C 4Misc 5Journal 73Unranked 49

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	CrossFetch: A Prefetching Scheme for Cross-Page Prefetching in the Physical Address Space. IEEE Comput. Archit. Lett. Qi Shao, Per Stenström
2025	—	`conf`	ASaP: Automatic Software Prefetching for Sparse Tensor Computations in MLIR. SC Workshops Konstantinos Sotiropoulos, Jonas Skeppstedt, Per Stenström
2025	—	`conf`	BATCH-DNN: Adaptive and Dynamic Batching for Multi-DNN Accelerators. Euro-Par (2) Piyumal Ranawaka, Per Stenström
2024	—	`conf`	DNNOPT: A Framework for Efficiently Selecting On-chip Memory Loop Optimizations of DNN Accelerators. CF Piyumal Ranawaka, Muhammad Waqar Azhar, Per Stenström
2024	A	`conf`	HMComp: Extending Near-Memory Capacity using Compression in Hybrid Memory. ICS Qi Shao, Angelos Arelakis, Per Stenström
2023	J	`jnl`	Approx-RM: Reducing Energy on Heterogeneous Multicore Processors under Accuracy and Timing Constraints. ACM Trans. Archit. Code Optim. Muhammad Waqar Azhar, Madhavan Manivannan, Per Stenström
2023	—	`conf`	SCALE: Secure and Scalable Cache Partitioning. HOST Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström
2023	A	`conf`	SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations. EuroS&P Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström
2023	—	`conf`	eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem. CF Lluc Alvarez, Abraham Ruiz, Arnau Bigas-Soldevilla, Pavel Kuroedov, Alberto González, Hamsika Mahale, Noe Bustamante, Albert Aguilera, Francesco Minervini, Javier Salamero, Oscar Palomar, Vassilis Papaefstathiou, Antonis Psathakis, Nikolaos Dimou, Michalis Giaourtas, Iasonas Mastorakis, Georgios Ieronymakis, Georgios-Michail Matzouranis, Vassilis Flouris, Nick Kossifidis, Manolis Marazakis, Bhavishya Goel, Madhavan Manivannan, Ahsen Ejaz, Panagiotis Strikos, Mateo Vázquez, Ioannis Sourdis, Pedro Trancoso, Per Stenström, Jens Hagemeyer, Lennart Tigges, Nils Kucza, Jean-Marc Philippe, Ioannis Papaefstathiou
2022	J	`jnl`	Bounding the execution time of parallel applications on unrelated multiprocessors. Real Time Syst. Petros Voudouris, Per Stenström, Risat Pathan
2022	J	`jnl`	Cooperative Slack Management: Saving Energy of Multicore Processors by Trading Performance Slack Between QoS-Constrained Applications. ACM Trans. Archit. Code Optim. Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
2022	A*	`conf`	GBDI: Going Beyond Base-Delta-Immediate Compression with Global Bases. HPCA Alexandra Angerd, Angelos Arelakis, Vasilis Spiliopoulos, Erik Sintorn, Per Stenström
2022	J	`jnl`	SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations. CoRR Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström
2022	J	`jnl`	Task-RM: A Resource Manager for Energy Reduction in Task-Parallel Applications under Quality of Service Constraints. ACM Trans. Archit. Code Optim. Muhammad Waqar Azhar, Miquel Pericàs, Per Stenström
2021	B	`conf`	CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling. PACT Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström, Miquel Pericàs
2021	J	`jnl`	CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling. CoRR Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström, Miquel Pericàs
2021	J	`jnl`	Federated Scheduling of Sporadic DAGs on Unrelated Multiprocessors. ACM Trans. Embed. Comput. Syst. Petros Voudouris, Per Stenström, Risat Pathan
2020	B	`conf`	A GPU Register File using Static Data Compression. ICPP Alexandra Angerd, Erik Sintorn, Per Stenström
2020	J	`jnl`	A GPU Register File using Static Data Compression. CoRR Alexandra Angerd, Erik Sintorn, Per Stenström
2020	A	`conf`	Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints. IPDPS Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
2020	J	`jnl`	Coordinated management of DVFS and cache partitioning under QoS constraints to save energy in multi-core systems. J. Parallel Distributed Comput. Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
2020	A	`conf`	DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors. IPDPS Nadja Holtryd, Madhavan Manivannan, Per Stenström, Miquel Pericàs
2019	—	`ed.`	Advanced Parallel Processing Technologies - 13th International Symposium, APPT 2019, Tianjin, China, August 15-16, 2019, Proceedings APPT Pen-Chung Yew, Per Stenström, Junjie Wu, Xiaoli Gong, Tao Li
2019	J	`jnl`	Coordinated Management of DVFS and Cache Partitioning under QoS Constraints to Save Energy in Multi-Core Systems. CoRR Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
2019	J	`jnl`	Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints. CoRR Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
2019	A	`conf`	QoS-Driven Coordinated Management of Resources to Save Energy in Multi-core Systems. IPDPS Mehrzad Nejat, Miquel Pericàs, Per Stenström
2019	B	`conf`	SaC: Exploiting Execution-Time Slack to Save Energy in Heterogeneous Multicore Systems. ICPP Muhammad Waqar Azhar, Miquel Pericàs, Per Stenström
2019	J	`jnl`	Trends on heterogeneous and innovative hardware and software systems. J. Parallel Distributed Comput. Alba de Melo, Jesús Carretero, Per Stenström, Sanjay Ranka, Eduard Ayguadé
2018	J	`jnl`	Global Dead-Block Management for Task-Parallel Programs. ACM Trans. Archit. Code Optim. Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström
2018	A*	`conf`	ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness. HPCA Dmitry Knyaginin, Vassilis Papaefstathiou, Per Stenström
2018	B	`ed.`	Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, PACT 2018, Limassol, Cyprus, November 01-04, 2018 PACT Skevos Evripidou, Per Stenström, Michael F. P. O'Boyle
2018	J	`jnl`	Scheduling Parallel Real-Time Recurrent Tasks on Multicore Platforms. IEEE Trans. Parallel Distributed Syst. Risat Pathan, Petros Voudouris, Per Stenström
2017	J	`jnl`	A Framework for Automated and Controlled Floating-Point Accuracy Reduction in Graphics Applications on GPUs. ACM Trans. Archit. Code Optim. Alexandra Angerd, Erik Sintorn, Per Stenström
2017	—	`conf`	Rock: a framework for pruning the design space of hybrid main memory systems. MEMSYS Dmitry Knyaginin, Per Stenström
2017	J	`jnl`	Runtime-Assisted Global Cache Management for Task-Based Parallel Programs. IEEE Comput. Archit. Lett. Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström
2017	J	`jnl`	SLOOP: QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures. ACM Trans. Archit. Code Optim. Muhammad Waqar Azhar, Per Stenström, Vassilis Papaefstathiou
2017	A	`conf`	Timing-Anomaly Free Dynamic Scheduling of Task-Based Parallel Applications. RTAS Petros Voudouris, Per Stenström, Risat Pathan
2016	J	`jnl`	2015 Maurice Wilkes Award Given to Christos Kozyrakis. IEEE Micro Per Stenström
2016	—	`conf`	Adaptive Row Addressing for Cost-Efficient Parallel Memory Protocols in Large-Capacity Memories. MEMSYS Dmitry Knyaginin, Vassilis Papaefstathiou, Per Stenström
2016	A	`conf`	EUROSERVER: Share-anything scale-out micro-server design. DATE Manolis Marazakis, John Goodacre, Didier Fuin, Paul M. Carpenter, John Thomson, Emil Matús, Antimo Bruno, Per Stenström, Jérôme Martin, Yves Durand, Isabelle Dor
2016	J	`jnl`	PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor. IEEE Comput. Archit. Lett. Minghua Li, Guancheng Chen, Qijun Wang, Yonghua Lin, H. Peter Hofstee, Per Stenström, Dian Zhou
2016	A*	`conf`	RADAR: Runtime-assisted dead region management for last-level caches. HPCA Madhavan Manivannan, Vassilis Papaefstathiou, Miquel Pericàs, Per Stenström
2016	A	`conf`	Timing-anomaly free dynamic scheduling of task-based parallel applications. RTSS Petros Voudouris, Per Stenström, Risat Pathan
2015	—	`book`	A Primer on Compression in the Memory Hierarchy Somayeh Sardashti, Angelos Arelakis, Per Stenström, David A. Wood
2015	B	`conf`	Enhancing Garbage Collection Synchronization Using Explicit Bit Barriers. ICPP Jochen Hollmann, J. Rubén Titos Gil, Per Stenström
2015	A*	`conf`	HyComp: a hybrid cache compression method for selection of data-type-specific compression methods. MICRO Angelos Arelakis, Fredrik Dahlgren, Per Stenström
2015	A	`conf`	Performance Impact of Batching Web-Application Requests Using Hot-Spot Processing on GPUs. IPDPS Tobias Fjalling, Per Stenström
2014	A	`ed.`	2014 International Conference on Supercomputing, ICS'14, Muenchen, Germany, June 10-13, 2014 ICS Arndt Bode, Michael Gerndt, Per Stenström, Lawrence Rauchwerger, Barton P. Miller, Martin Schulz
2014	J	`jnl`	A Case for a Value-Aware Cache. IEEE Comput. Archit. Lett. Angelos Arelakis, Per Stenström
2014	J	`jnl`	Characterizing and Exploiting Small-Value Memory Instructions. IEEE Trans. Computers Mafijul Md. Islam, Per Stenström
2014	B	`conf`	Crystal: A Design-Time Resource Partitioning Method for Hybrid Main Memory. ICPP Dmitry Knyaginin, Georgi Gaydadjiev, Per Stenström
2014	A	`conf`	Effective resource management towards efficient computing. DATE Per Stenström
2014	J	`jnl`	Introduction to the JPDC special issue on Perspectives on Parallel and Distributed Processing. J. Parallel Distributed Comput. Viktor K. Prasanna, Yves Robert, Per Stenström
2014	A	`conf`	Overhead-aware temporal partitioning on multicore processors. RTAS Risat Mahmud Pathan, Per Stenström, Lars-Goran Green, Torbjorn Hult, Patrik Sandin
2014	A	`conf`	Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell. IPDPS Bhavishya Goel, J. Rubén Titos Gil, Anurag Negi, Sally A. McKee, Per Stenström
2014	J	`jnl`	Removal of Conflicts in Hardware Transactional Memory Systems. Int. J. Parallel Program. M. M. Waliullah, Per Stenström
2014	A	`conf`	Runtime-Guided Cache Coherence Optimizations in Multi-core Architectures. IPDPS Madhavan Manivannan, Per Stenström
2014	A*	`conf`	SC ISCA Angelos Arelakis, Per Stenström
2014	J	`jnl`	ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström
2013	J	`jnl`	Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström
2013	B	`conf`	Efficient Forwarding of Producer-Consumer Data in Task-Based Programs. ICPP Madhavan Manivannan, Anurag Negi, Per Stenström
2013	Misc	`conf`	HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory. HiPC Adrià Armejach, Anurag Negi, Adrián Cristal, Osman S. Unsal, Per Stenström, Tim Harris
2013	A	`conf`	Improving data access efficiency by using a tagless access buffer (TAB). CGO Alen Bardizbanyan, Peter Gavin, David B. Whalley, Magnus Själander, Per Larsson-Edefors, Sally A. McKee, Per Stenström
2013	B	`conf`	Keynote talk: Towards automatic resource management in parallel architectures. PACT Per Stenström
2013	J	`jnl`	Moving from petaflops to petadata. Commun. ACM Michael J. Flynn, Oskar Mencer, Veljko M. Milutinovic, Goran Rakocevic, Per Stenström, Roman Trobec, Mateo Valero
2012	A	`conf`	Critical lock analysis: diagnosing critical section bottlenecks in multithreaded applications. SC Guancheng Chen, Per Stenström
2012	J	`jnl`	Introduction to the special issue on high-performance and embedded architectures and compilers. ACM Trans. Archit. Code Optim. Per Stenström, Koen De Bosschere
2012	B	`conf`	Transactional prefetching: narrowing the window of contention in hardware transactional memory. PACT Anurag Negi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Per Stenström
2012	A*	`conf`	π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory. HPCA Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström
2011	Misc	`conf`	A unified approach to eliminate memory accesses early. CASES Mafijul Md. Islam, Per Stenström
2011	C	`conf`	Classification and Elimination of Conflicts in Hardware Transactional Memory Systems. SBAC-PAD Mridha-Mohammad Waliullah, Per Stenström
2011	B	`conf`	Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory. ICPP Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström
2011	B	`conf`	Implications of Merging Phases on Scalability of Multi-core Architectures. ICPP Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström
2011	A	`conf`	Panel Statement. IPDPS Per Stenström, Doug Burger, Wen-mei W. Hwu, Vipin Kumar, Kunle Olukotun, David A. Padua, Burton Smith
2011	B	`conf`	Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory. PACT Anurag Negi, Per Stenström, J. Rubén Titos Gil, Manuel E. Acacio, José M. García
2011	A	`conf`	Poster: implications of merging phases on scalability of multi-core architectures. ICS Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström
2011	—	`conf`	The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems. IPDPS Workshops Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström
2011	—	`ed.`	Transactions on High-Performance Embedded Architectures and Compilers III Trans. HiPEAC Per Stenström
2011	—	`ed.`	Transactions on High-Performance Embedded Architectures and Compilers IV Trans. HiPEAC Per Stenström
2011	A	`conf`	ZEBRA: a data-centric, hybrid-policy hardware transactional memory design. ICS J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström
2010	Misc	`conf`	Characterization and exploitation of narrow-width loads: the narrow-width cache approach. CASES Mafijul Md. Islam, Per Stenström
2010	—	`conf`	LV ICSAMOS Anurag Negi, M. M. Waliullah, Per Stenström
2010	—	`conf`	LV*: a class of lazy versioning HTMs for low-cost integration of transactional memory systems. IFMT Anurag Negi, M. M. Waliullah, Per Stenström
2010	J	`jnl`	The Velox Transactional Memory Stack. IEEE Micro Yehuda Afek, Ulrich Drepper, Pascal Felber, Christof Fetzer, Vincent Gramoli, Michael Hohmuth, Etienne Rivière, Per Stenström, Osman S. Unsal, Walther Maldonado, Derin Harmanci, Patrick Marlier, Stephan Diestelhorst, Martin Pohlack, Adrián Cristal, Ibrahim Hur, Aleksandar Dragojevic, Rachid Guerraoui, Michal Kapalka, Sasa Tomic, Guy Korland, Nir Shavit, Martin Nowack, Torvald Riegel
2009	—	`conf`	A Flexible Code Compression Scheme Using Partitioned Look-Up Tables. HiPEAC Martin Thuresson, Magnus Själander, Per Stenström
2009	A	`conf`	Cancellation of loads that return zero using zero-value caches. ICS Md. Mafijul Islam, Sally A. McKee, Per Stenström
2009	J	`jnl`	FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. J. Signal Process. Syst. Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström
2009	J	`jnl`	Introduction. Trans. High Perform. Embed. Archit. Compil. Per Stenström, David B. Whalley
2009	J	`jnl`	Schemes for avoiding starvation in transactional memory systems. Concurr. Comput. Pract. Exp. M. M. Waliullah, Per Stenström
2009	—	`ed.`	Transactions on High-Performance Embedded Architectures and Compilers II Trans. HiPEAC Per Stenström
2009	—	`conf`	Using Hoarding to Increase Availability in Shared File Systems. ACIS-ICIS Jochen Hollmann, Per Stenström
2009	B	`conf`	Zero-Value Caches: Cancelling Loads that Return Zero. PACT Md. Mafijul Islam, Per Stenström
2008	B	`conf`	Accommodation of the Bandwidth of Large Cache Blocks Using Cache/Memory Link Compression. ICPP Martin Thuresson, Per Stenström
2008	J	`jnl`	Dual-thread Speculation: A Simple Approach to Uncover Thread-level Parallelism on a Simultaneous Multithreaded Processor. Int. J. Parallel Program. Fredrik Warg, Per Stenström
2008	J	`jnl`	Early detection and bypassing of trivial operations to improve energy efficiency of processors. Microprocess. Microsystems Md. Mafijul Islam, Magnus Själander, Per Stenström
2008	—	`conf`	Efficient management of speculative data in hardware transactional memory systems. ICSAMOS M. M. Waliullah, Per Stenström
2008	—	`ed.`	High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings HiPEAC Per Stenström, Michel Dubois, Manolis Katevenis, Rajiv Gupta, Theo Ungerer
2008	A	`conf`	Intermediate checkpointing with conflicting access prediction in transactional memory systems. IPDPS M. M. Waliullah, Per Stenström
2008	C	`conf`	Leveraging Data Promotion for Low Power D-NUCA Caches. DSD Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Per Stenström
2008	J	`jnl`	Memory-Link Compression Schemes: A Value Locality Perspective. IEEE Trans. Computers Martin Thuresson, Lawrence Spracklen, Per Stenström
2008	J	`jnl`	Simple Penalty-Sensitive Cache Replacement Policies. J. Instr. Level Parallelism Jaeheon Jeong, Per Stenström, Michel Dubois
2008	J	`jnl`	The worst-case execution-time problem - overview of methods and survey of tools. ACM Trans. Embed. Comput. Syst. Reinhard Wilhelm, Jakob Engblom, Andreas Ermedahl, Niklas Holsti, Stephan Thesing, David B. Whalley, Guillem Bernat, Christian Ferdinand, Reinhold Heckmann, Tulika Mitra, Frank Mueller, Isabelle Puaut, Peter P. Puschner, Jan Staschulat, Per Stenström
2008	—	`conf`	Zero loads: canceling load requests by tracking zero values. MEDEA@PACT Mafijul Md. Islam, Per Stenström
2007	A*	`conf`	An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors. HPCA Haakon Dybdahl, Per Stenström
2007	J	`jnl`	An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches. SIGARCH Comput. Archit. News Haakon Dybdahl, Per Stenström, Lasse Natvig
2007	—	`conf`	Characterization of Apache web server with Specweb2005. MEDEA@PACT Ana Bosque, Pablo Ibáñez, Víctor Viñals, Per Stenström, José María Llabería
2007	J	`jnl`	Effectiveness of caching in a distributed digital library system. J. Syst. Archit. Jochen Hollmann, Anders Ardö, Per Stenström
2007	—	`conf`	Energy and Performance Trade-offs between Instruction Reuse and Trivial Computations for Embedded Applications. SIES Md. Mafijul Islam, Per Stenström
2007	—	`conf`	FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. ICSAMOS Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström
2007	—	`ed.`	High Performance Embedded Architectures and Compilers, Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings HiPEAC Koen De Bosschere, David R. Kaeli, Per Stenström, David B. Whalley, Theo Ungerer
2007	J	`jnl`	High-Performance Embedded Architecture and Compilation Roadmap. Trans. High Perform. Embed. Archit. Compil. Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Michael F. P. O'Boyle, Dionisios N. Pnevmatikatos, Alex Ramírez, Pascal Sainrat, André Seznec, Per Stenström, Olivier Temam
2007	A	`conf`	IPDPS Panel: Is the Multi-Core Roadmap going to Live Up to its Promises? IPDPS Per Stenström
2007	—	`conf`	Implicit Transactional Memory in Kilo-Instruction Multiprocessors. Asia-Pacific Computer Systems Architecture Conference Marco Galluzzi, Enrique Vallejo, Adrián Cristal, Fernando Vallejo, Ramón Beivide, Per Stenström, James E. Smith, Mateo Valero
2007	J	`jnl`	Improving power efficiency of D-NUCA caches. SIGARCH Comput. Archit. News Alessandro Bardine, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Per Stenström
2007	J	`jnl`	Introduction to Part 1. Trans. High Perform. Embed. Archit. Compil. Per Stenström
2007	B	`conf`	Loop-level Speculative Parallelism in Embedded Applications. ICPP Md. Mafijul Islam, Alexander Busck, Mikael Engbom, Simji Lee, Michel Dubois, Per Stenström
2007	A	`conf`	Microprocessors in the era of terascale integration. DATE Shekhar Borkar, Norman P. Jouppi, Per Stenström
2007	—	`ed.`	Proceedings of the 4th Conference on Computing Frontiers, 2007, Ischia, Italy, May 7-9, 2007 Conf. Computing Frontiers Utpal Banerjee, José Moreira, Michel Dubois, Per Stenström
2007	J	`jnl`	SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators. IEEE Micro Jianwei Chen, Michel Dubois, Per Stenström
2007	—	`conf`	Starvation-Free Transactional Memory-System Protocols. Euro-Par M. M. Waliullah, Per Stenström
2007	J	`jnl`	Starvation-free commit arbitration policies for transactional memory systems. SIGARCH Comput. Archit. News M. M. Waliullah, Per Stenström
2007	—	`ed.`	Transactions on High-Performance Embedded Architectures and Compilers I Trans. HiPEAC Per Stenström, Michael F. P. O'Boyle, François Bodin, Marcelo Cintra, Sally A. McKee
2006	Misc	`conf`	A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors. HiPC Haakon Dybdahl, Per Stenström, Lasse Natvig
2006	—	`conf`	An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches. MEDEA@PACT Haakon Dybdahl, Per Stenström, Lasse Natvig
2006	A*	`conf`	Chip-multiprocessing and beyond. HPCA Per Stenström
2006	C	`conf`	Dual-Thread Speculation: Two Threads in the Machine are Worth Eight in the Bush. SBAC-PAD Fredrik Warg, Per Stenström
2006	—	`conf`	Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination. Asia-Pacific Computer Systems Architecture Conference Haakon Dybdahl, Per Stenström
2006	J	`jnl`	Introduction. J. Parallel Distributed Comput. Burkhard Monien, Guang Gao, Horst D. Simon, Paul G. Spirakis, Per Stenström
2006	—	`conf`	Reduction of Energy Consumption in Processors by Early Detection and Bypassing of Trivial Operations. ICSAMOS Md. Mafijul Islam, Per Stenström
2006	C	`conf`	Scalable Value-Cache Based Compression Schemes for Multiprocessors. SBAC-PAD Martin Thuresson, Per Stenström
2006	—	`conf`	Simple penalty-sensitive replacement policies for caches. Conf. Computing Frontiers Jaeheon Jeong, Per Stenström, Michel Dubois
2005	A	`conf`	A Cost-Effective Main Memory Organization for Future Servers. IPDPS Magnus Ekman, Per Stenström
2005	A*	`conf`	A Robust Main-Memory Compression Scheme. ISCA Magnus Ekman, Per Stenström
2005	B	`conf`	Enhancing Multiprocessor Architecture Simulation Speed Using Matched-Pair Comparison. ISPASS Magnus Ekman, Per Stenström
2005	—	`conf`	Evaluation of extended dictionary-based static code compression schemes. Conf. Computing Frontiers Martin Thuresson, Per Stenström
2005	—	`conf`	Implementing Kilo-Instruction Multiprocessors. ICPS Enrique Vallejo, Marco Galluzzi, Adrián Cristal, Fernando Vallejo, Ramón Beivide, Per Stenström, James E. Smith, Mateo Valero
2005	J	`jnl`	Introduction to the special issue. ACM Trans. Embed. Comput. Syst. Frank Mueller, Per Stenström
2005	—	`conf`	Reducing misspeculation overhead for module-level speculative execution. Conf. Computing Frontiers Fredrik Warg, Per Stenström
2005	—	`conf`	The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges. HiPEAC Per Stenström
2004	J	`jnl`	A cache block reuse prediction scheme. Microprocess. Microsystems Jonas Jalminger, Per Stenström
2004	—	`conf`	A case for multi-level main memory. WMPI Magnus Ekman, Per Stenström
2004	J	`jnl`	A comparative evaluation of hardware-only and software-only directory protocols in shared-memory multiprocessors. J. Syst. Archit. Håkan Grahn, Per Stenström
2004	—	`conf`	Self-correcting LRU replacement policies. Conf. Computing Frontiers Martin Kämpe, Per Stenström, Michel Dubois
2003	B	`conf`	A Novel Approach to Cache Block Reuse Predictions. ICPP Jonas Jalminger, Per Stenström
2003	—	`conf`	An Evaluation of Document Prefetching in a Distributed Digital Library. ECDL Jochen Hollmann, Anders Ardö, Per Stenström
2003	A	`conf`	Improving Speculative Thread-Level Parallelism Through Module Run-Length Prediction. IPDPS Fredrik Warg, Per Stenström
2003	B	`conf`	Integrating complete-system and user-level performance/power simulators: the SimWattch approach. ISPASS Jianwei Chen, Michel Dubois, Per Stenström
2003	Misc	`conf`	One Chip, One Server: How Do We Exploit Its Power? HiPC Per Stenström
2003	B	`conf`	Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores. ICPP Magnus Ekman, Per Stenström
2003	A	`conf`	Speculative Lock Reordering: Optimistic Out-of-Order Execution of Critical Sections. IPDPS Peter Rundberg, Per Stenström
2003	A	`conf`	The Coherence Predictor Cache: A Resource-Efficient and Accurate Coherence Prediction Infrastructure. IPDPS Jim Nilsson, Anders Landin, Per Stenström
2002	A	`conf`	Empirical Observations Regarding Predictability in User Access-Behavior in a Distributed Digital Library System. IPDPS Jochen Hollmann, Anders Ardö, Per Stenström
2002	J	`jnl`	Improvement of energy-efficiency in off-chip caches by selective prefetching. Microprocess. Microsystems Jonas Jalminger, Per Stenström
2002	A	`conf`	TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors. ISLPED Magnus Ekman, Per Stenström, Fredrik Dahlgren
2002	A*	`conf`	The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches. HPCA Martin Kämpe, Per Stenström, Michel Dubois
2001	—	`conf`	A Case Study of Load Distribution in Parallel View Frustum Culling and Collision Detection. Euro-Par Ulf Assarsson, Per Stenström
2001	J	`jnl`	An All-Software Thread-Level Data Dependence Speculation System for Multiprocessors. J. Instr. Level Parallelism Peter Rundberg, Per Stenström
2001	—	`conf`	Limits on Speculative Module-Level Parallelism in Imperative and Object-Oriented Programs on CMP Platforms. IEEE PACT Fredrik Warg, Per Stenström
2001	A*	`ed.`	Proceedings of the 28th Annual International Symposium on Computer Architecture, ISCA 2001, Göteborg, Sweden, June 30-July 4, 2001 ISCA Per Stenström
2000	A*	`conf`	A Prefetching Technique for Irregular Accesses to Linked Data Structures. HPCA Magnus Karlsson, Fredrik Dahlgren, Per Stenström
2000	A*	`conf`	An analytical model of the working-set sizes in decision-support systems. SIGMETRICS Magnus Karlsson, Per Stenström
2000	J	`jnl`	Comparative Evaluation of Latency-Tolerating and -Reducing Techniques for Hardware-Only and Software-Only Directory Protocols. J. Parallel Distributed Comput. Håkan Grahn, Per Stenström
2000	—	`conf`	Parallel Computer Architecture. Euro-Par Silvia M. Müller, Per Stenström, Mateo Valero, Stamatis Vassiliadis
2000	A*	`conf`	Recency-based TLB preloading. ISCA Ashley Saulsbury, Fredrik Dahlgren, Per Stenström
2000	J	`jnl`	Shared-memory multiprocessing: Current state and future directions. Adv. Comput. Per Stenström, Erik Hagersten, David J. Lilja, Margaret Martonosi, Madan Venugopal
1999	B	`conf`	A Method to Improve the Estimated Worst-Case Performance of Data Caching. RTCSA Thomas Lundqvist, Per Stenström
1999	J	`jnl`	An Integrated Path and Timing Analysis Method based on Cycle-Level Symbolic Execution. Real Time Syst. Thomas Lundqvist, Per Stenström
1999	J	`jnl`	Evaluation of Compiler-Controlled Updating to Reduce Coherence-Miss Penalties in Shared-Memory Multiprocessors. J. Parallel Distributed Comput. Jonas Skeppstedt, Fredrik Dahlgren, Per Stenström
1999	J	`jnl`	Special Issue On Distributed Shared Memory Systems. Proc. IEEE Veljko Milutinovic, Per Stenström
1999	A	`conf`	Timing Anomalies in Dynamically Scheduled Microprocessors. RTSS Thomas Lundqvist, Per Stenström
1998	—	`conf`	A holistic approach to computer system design education based on system simulation techniques. WCAE@ISCA Per Stenström, Fredrik Dahlgren
1998	J	`jnl`	An evaluation of hardware-based and compiler-controlled optimizations of snooping cache protocols. Future Gener. Comput. Syst. Fredrik Dahlgren, Jonas Skeppstedt, Per Stenström
1998	B	`conf`	Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques. LCTES Thomas Lundqvist, Per Stenström
1998	J	`jnl`	Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors. IEEE Trans. Computers Fredrik Dahlgren, Michel Dubois, Per Stenström
1998	—	`conf`	SimICS/Sun4m: A Virtual Workstation. USENIX ATC Peter S. Magnusson, Fredrik Larsson, Andreas Moestedt, Bengt Werner, Jim Nilsson, Per Stenström, Fredrik Lundholm, Magnus Karlsson, Fredrik Dahlgren, Håkan Grahn
1997	—	`conf`	A Performance Tuning Approach for Shared-Memory Multiprocessors. Euro-Par Per Stenström, Jonas Skeppstedt
1997	J	`jnl`	Boosting the Performance of Shared Memory Multiprocessors. Computer Per Stenström, Mats Brorsson, Fredrik Dahlgren, Håkan Grahn, Michel Dubois
1997	J	`jnl`	Effectivness of Dynamic Prefetching in Multiple-Writer Distributed Virtual Shared-Memory Systems. J. Parallel Distributed Comput. Magnus Karlsson, Per Stenström
1997	J	`jnl`	Reducing the Read-Miss Penalty for Flat COMA Protocols. Comput. J. Fredrik Dahlgren, Per Stenström, Mårten Björkman
1997	—	`conf`	Relative Performance of Hardware and Software-Only Directory Protocols Under Latency Tolerating and Reducing Techniques. IPPS Håkan Grahn, Per Stenström
1997	J	`jnl`	Trends in Shared Memory Multiprocessing. Computer Per Stenström, Erik Hagersten, David J. Lilja, Margaret Martonosi, Madan Venugopal
1996	J	`jnl`	Applications for Shared Memory Multiprocessors (Guest Editors' Introduction). Computer Per Stenström, Fredrik Dahlgren
1996	J	`jnl`	Characterising and Modelling Shared Memory Accesses in Multiprocessor Programs. Parallel Comput. Mats Brorsson, Per Stenström
1996	J	`jnl`	Evaluation of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. IEEE Trans. Parallel Distributed Syst. Fredrik Dahlgren, Per Stenström
1996	J	`jnl`	Evaluation of a Competitive-Update Cache Coherence Protocol with Migratory Data Detection. J. Parallel Distributed Comput. Håkan Grahn, Per Stenström
1996	A*	`conf`	Performance Evaluation of a Cluster-Based Multiprocessor Built from ATM Switches and Bus-Based Multiprocessor Servers. HPCA Magnus Karlsson, Per Stenström
1996	J	`jnl`	The design of a non-blocking load processor architecture. Microprocess. Microsystems Per Stenström, Magnus Balldin, Jonas Skeppstedt
1996	J	`jnl`	Using Dataflow Analysis Techniques to Reduce Ownership Overhead in Cache Coherence Protocols. ACM Trans. Program. Lang. Syst. Jonas Skeppstedt, Per Stenström
1995	B	`conf`	A compiler algorithm that reduces read latency in ownership-based cache coherence protocols. PACT Jonas Skeppstedt, Per Stenström
1995	A*	`conf`	Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. HPCA Fredrik Dahlgren, Per Stenström
1995	A*	`conf`	Efficient Strategies for Software-Only Protocols in Shared-Memory Multiprocessors. ISCA Håkan Grahn, Per Stenström
1995	J	`jnl`	Essential Misses and Data Traffic in Coherence Protocols. J. Parallel Distributed Comput. Michel Dubois, Jonas Skeppstedt, Per Stenström
1995	J	`jnl`	Implementation and evaluation of update-based cache protocols under relaxed memory consistency models. Future Gener. Comput. Syst. Håkan Grahn, Per Stenström, Michel Dubois
1995	J	`jnl`	Sequential Hardware Prefetching in Shared-Memory Multiprocessors. IEEE Trans. Parallel Distributed Syst. Fredrik Dahlgren, Michel Dubois, Per Stenström
1995	J	`jnl`	Using Write Caches to Improve Performance of Cache Coherence Protocols in Shared-Memory Multiprocessors. J. Parallel Distributed Comput. Fredrik Dahlgren, Per Stenström
1995	—	`conf`	Using hints to reduce the read miss penalty for flat COMA protocols. HICSS (1) Mårten Björkman, Fredrik Dahlgren, Per Stenström
1994	—	`conf`	An Adaptive Update-Based Cache Coherence Protocol for Reduction of Miss Rate and Traffic. PARLE Håkan Nilsson, Per Stenström
1994	—	`conf`	An Integrated Methodology for the Verification of Directory-Based Cache Protocols. ICPP (1) Fong Pong, Per Stenström, Michel Dubois
1994	A*	`conf`	Combined Performance Gains of Simple Cache Protocol Extensions. ISCA Fredrik Dahlgren, Michel Dubois, Per Stenström
1994	—	`conf`	Introduction. HICSS (1) Per Stenström
1994	—	`conf`	Modelling accesses to migratory and producer-consumer characterised data in a shared memory multiprocessor. SPDP Mats Brorsson, Per Stenström
1994	—	`conf`	Reducing the Write Traffic for a Hybrid Cache Protocol. ICPP (1) Fredrik Dahlgren, Per Stenström
1994	A*	`conf`	Simple Compiler Algorithms to Reduce Ownership Operhead in Cache Coherence Protocols. ASPLOS Jonas Skeppstedt, Per Stenström
1993	A*	`conf`	An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing. ISCA Per Stenström, Mats Brorsson, Lars Sandberg
1993	—	`conf`	Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors. ICPP (1) Fredrik Dahlgren, Michel Dubois, Per Stenström
1993	—	`conf`	The Cachemire Test Bench A Flexible And Effective Approach For Simulation Of Multiprocessors. Annual Simulation Symposium Mats Brorsson, Fredrik Dahlgren, Håkan Nilsson, Per Stenström
1993	A*	`conf`	The Detection and Elimination of Useless Misses in Multiprocessors. ISCA Michel Dubois, Jonas Skeppstedt, Livio Ricciulli, Krishnan Ramamurthy, Per Stenström
1992	—	`conf`	A Latency-Hiding Scheme for Multiprocessors with Buffered Multistage Networks. IPPS Per Stenström
1992	A*	`conf`	Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures. ISCA Per Stenström, Truman Joe, Anoop Gupta
1992	—	`conf`	The Scalable Tree Protocol - A Cache Coherence Approach for Large-Scale Multiprocessors. SPDP Håkan Nilsson, Per Stenström
1991	—	`conf`	A Lockup-Free Multiprocessor Cache Design. ICPP (1) Per Stenström, Fredrik Dahlgren, Lars Lundberg
1991	A*	`conf`	On Reconfigurable On-Chip Data Caches. MICRO Fredrik Dahlgren, Per Stenström
1990	J	`jnl`	A Survey of Cache Coherence Schemes for Multiprocessors. Computer Per Stenström
1989	A*	`conf`	A Cache Consistency Protocol for Multiprocessors with Multistage Networks. ISCA Per Stenström
1988	J	`jnl`	Reducing Contention in Sharde-Memory Multiprocessors. Computer Per Stenström
1987	—	`conf`	A Layered Emulator for Design Evaluation of MIMD Multiprocessors with Shared Memory. PARLE (1) Per Stenström, Lars H. Philipson