Per Larsson-Edefors

118 papers A 5B 1C 17Misc 2Journal 13Unranked 80
YearRankTypeTitle / Venue / Authors
2025 — conf
Activity-Based Input Operand Assignment for Reduced Multiplier Power Dissipation.
LASCAS
Per Larsson-Edefors, Erik Börjeson
2025 — conf
DSP Hardware Tradeoffs for Digital Predistortion based on Pruned Volterra Series.
SiPS
Mubanda Talemwa, Jorge Muñoz Bautista, Thomas Eriksson, Per Larsson-Edefors
2025 C conf
Energy-Efficient Computation of TensorFloat32 Numbers on an FP32 Multiplier.
VLSI-SoC
Per Larsson-Edefors
2025 C conf
FPGA-Based Wordlength Optimization for DSP.
ISCAS
Chenhao Yang, Jinsheng Bian, Erik Börjeson, Per Larsson-Edefors
2025 C conf
Implementation Evaluation of Fixed-Point Multipliers for Complex Numbers.
ARITH
Per Larsson-Edefors, Erik Börjeson
2025 C conf
Low-Power Complex Multiplier Pin Assignment Based on Spatial and Temporal Signal Properties.
ISCAS
Per Larsson-Edefors, Erik Börjeson
2024 — conf
Circuit Implementation of Pilot-Based Dynamic MIMO Equalization for Coupled-Core Fibers.
OFC
Erik Börjeson, Ekaterina Deriushkina, Mikael Mazur, Magnus Karlsson, Per Larsson-Edefors
2024 — conf
Real-Time Implementation of Machine-Learning DSP.
OFC
Erik Börjeson, Keren Liu, Christian Häger, Per Larsson-Edefors
2024 — conf
Real-Time Monitoring of Cable Break in a Live Network using a Coherent Transceiver Prototype.
OFC
Mikael Mazur, Dennis Wallberg, Lauren Dallachiesa, Erik Börjeson, Roland Ryf, Magnus Bergroth, Börje Josefsson, Nicolas K. Fontaine, Haoshuo Chen, David T. Neilson, Jochen Schröder, Per Larsson-Edefors, Magnus Karlsson
2024 — conf
Unfolded SiBM BCH Decoders for High- Throughput Low-Latency Applications.
ISVLSI
Xu Wang, Christoffer Fougstedt, Lars J. Svensson, Per Larsson-Edefors
2023 — conf
FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training.
OFC
Keren Liu, Erik Börjeson, Christian Häger, Per Larsson-Edefors
2023 — conf
Field Trial of FPGA-Based Real-Time Sensing Transceiver over 524 km of Live Aerial Fiber.
OFC
Mikael Mazur, Dennis Wallberg, Lauren Dallachiesa, Erik Börjeson, Roland Ryf, Magnus Bergroth, Börje Josefsson, Nicolas K. Fontaine, Haoshuo Chen, David T. Neilson, Jochen Schröder, Per Larsson-Edefors, Magnus Karlsson
2022 J jnl
FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training.
CoRR
Keren Liu, Erik Börjeson, Christian Häger, Per Larsson-Edefors
2022 — conf
Fiber-on-Chip: Digital FPGA Emulation of Channel Impairments for Real-Time Evaluation of DSP.
OFC
Per Larsson-Edefors, Erik Börjeson
2022 — conf
Real-Time MIMO Transmission over Field-Deployed Coupled-Core Multi-Core Fibers.
OFC
Mikael Mazur, Roland Ryf, Nicolas K. Fontaine, Andrea Marotta, Erik Börjeson, Lauren Dallachiesa, Haoshuo Chen, Tetsuya Hayashi, Takuji Nagashima, Tetsuya Nakanishi, Tetsu Morishima, Fabio Graziosi, Luca Palmieri, David T. Neilson, Per Larsson-Edefors, Antonio Mecozzi, Cristian Antonelli
2022 — conf
Real-Time Transmission over 2×55 km All 7-Core Coupled-Core Multi-Core Fiber Link.
OFC
Mikael Mazur, Lauren Dallachiesa, Nicolas K. Fontaine, Roland Ryf, Erik Börjeson, Haoshuo Chen, Hirotaka Sakuma, Takafumi Ohtsuka, Tetsuya Hayashi, Takemi Hasegawa, Hidehisa Tazawa, David T. Neilson, Per Larsson-Edefors
2022 — conf
Transoceanic Phase and Polarization Fiber Sensing using Real-Time Coherent Transceiver.
OFC
Mikael Mazur, Jorge C. Castellanos, Roland Ryf, Erik Börjeson, Tracy Chodkiewicz, Valey Kamalov, Shuang Yin, Nicolas K. Fontaine, Haoshuo Chen, Lauren Dallachiesa, Steve Corteselli, Philip Copping, Jürgen Gripp, Aurelien Mortelette, Benoit Kowalski, Rodney Dellinger, David T. Neilson, Per Larsson-Edefors
2022 — conf
Waveform Memory for Real-Time FPGA Test of Fiber-Optic Receiver DSPs.
NorCAS
Rafael Romón Sagredo, Erik Börjeson, Ali Mirani, Magnus Karlsson, Per Larsson-Edefors
2021 — conf
Benchmarking of Carrier Phase Recovery Circuits for M-QAM Coherent Systems.
OFC
Erik Börjeson, Per Larsson-Edefors
2021 J jnl
Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder.
IEEE Trans. Circuits Syst. I Regul. Pap.
Vikram Jain, Christoffer Fougstedt, Per Larsson-Edefors
2020 — conf
ASIC Design Exploration for DSP and FEC of 400-Gbit/s Coherent Data-Center Interconnect Receivers.
OFC
Christoffer Fougstedt, Oscar Gustafsson, Cheolyong Bae, Erik Börjeson, Per Larsson-Edefors
2020 — conf
Cycle-Slip Rate Analysis of Blind Phase Search DSP Circuit Implementations.
OFC
Erik Börjeson, Per Larsson-Edefors
2019 — conf
ASIC Design Exploration of Phase Recovery Algorithms for M-QAM Fiber-Optic Systems.
OFC
Erik Börjeson, Christoffer Fougstedt, Per Larsson-Edefors
2019 — conf
Energy-Efficient Soft-Assisted Product Decoders.
OFC
Christoffer Fougstedt, Alireza Sheikh, Alexandre Graell i Amat, Gianluigi Liva, Per Larsson-Edefors
2019 C conf
Hardware Considerations for Selection Networks.
VLSI-SoC
Kenneth Peter, Lars J. Svensson, Christoffer Fougstedt, Per Larsson-Edefors
2019 — conf
Variable-Rate FEC Decoder VLSI Architecture for 400G Rate-Adaptive Optical Communication.
ICECS
Vikram Jain, Christoffer Fougstedt, Per Larsson-Edefors
2018 — conf
A High-Throughput Low-Power Soft Bit-Flipping LDPC Decoder in 28 nm FD-SOI.
ESSCIRC
Kevin Cushon, Per Larsson-Edefors, Peter A. Andrekson
2018 — conf
ASIC Implementation of Time-Domain Digital Backpropagation with Deep-Learned Chromatic Dispersion Filters.
ECOC
Christoffer Fougstedt, Christian Häger, Lars J. Svensson, Henry D. Pfister, Per Larsson-Edefors
2018 J jnl
ASIC Implementation of Time-Domain Digital Backpropagation with Deep-Learned Chromatic Dispersion Filters.
CoRR
Christoffer Fougstedt, Christian Häger, Lars J. Svensson, Henry D. Pfister, Per Larsson-Edefors
2018 — conf
Custom versus Cell-Based ASIC Design for Many-Channel Correlators.
SiPS
Erik Ryman, Christoffer Fougstedt, Lars J. Svensson, Per Larsson-Edefors
2018 — conf
Energy-Efficient High-Throughput Staircase Decoders.
OFC
Christoffer Fougstedt, Per Larsson-Edefors
2018 J jnl
Energy-Efficient Soft-Assisted Product Decoders.
CoRR
Christoffer Fougstedt, Alireza Sheikh, Alexandre Graell i Amat, Gianluigi Liva, Per Larsson-Edefors
2018 — conf
Power Consumption Savings Through Joint Carrier Recovery for Spectral and Spatial Superchannels.
ECOC
Lars Lundberg, Erik Börjeson, Christoffer Fougstedt, Mikael Mazur, Magnus Karlsson, Peter A. Andrekson, Per Larsson-Edefors
2017 — conf
A 3-GHz reconfigurable 2/3-level 96/48-channel cross-correlator for synthetic aperture radiometry.
ESSCIRC
Erik Ryman, Anders Emrich, Lars J. Svensson, Per Larsson-Edefors
2017 — conf
A framework for a relative real-time tracking system based on ultra-wideband technology.
WPNC
Gabriel Ortiz, Fredrik Treven, Lars J. Svensson, Per Larsson-Edefors, Sebastian Johansson-Mauricio
2017 — conf
Finite-Precision Optimization of Time-Domain Digital Back Propagation by Inter-Symbol Interference Minimization.
ECOC
Christoffer Fougstedt, Lars J. Svensson, Mikael Mazur, Magnus Karlsson, Per Larsson-Edefors
2017 — conf
Improved Low-Power LDPC FEC for Coherent Optical Systems.
ECOC
Kevin Cushon, Per Larsson-Edefors, Peter A. Andrekson
2017 — conf
Instruction level energy model for the Adapteva Epiphany multi-core processor.
Conf. Computing Frontiers
Gabriel Ortiz, Lars J. Svensson, Erik Alveflo, Per Larsson-Edefors
2017 — conf
Time-domain digital back propagation: Algorithm and finite-precision implementation aspects.
OFC
Christoffer Fougstedt, Mikael Mazur, Lars J. Svensson, Henrik Eliasson, Magnus Karlsson, Per Larsson-Edefors
2016 — conf
Dynamic equalizer power dissipation optimization.
OFC
Christoffer Fougstedt, Pontus Johannisson, Lars J. Svensson, Per Larsson-Edefors
2016 — conf
Logic filter cache for wide-VDD-range processors.
ICECS
Alen Bardizbanyan, Oskar Andersson, Joachim Neves Rodrigues, Per Larsson-Edefors
2016 A conf
Practical way halting by speculatively accessing halt tags.
DATE
Daniel Moreau, Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors
2016 Misc conf
Redesigning a tagless access buffer to require minimal ISA changes.
CASES
Carlos Sanchez, Peter Gavin, Daniel Moreau, Magnus Själander, David B. Whalley, Per Larsson-Edefors, Sally A. McKee
2015 — conf
Energy-efficient soft-decision LDPC FEC For long-haul optical communication.
ECOC
Kevin Cushon, Per Larsson-Edefors, Peter A. Andrekson
2015 C conf
Exploring early and late ALUs for single-issue in-order pipelines.
ICCD
Alen Bardizbanyan, Per Larsson-Edefors
2015 — conf
Impact of forward error correction on energy consumption of VCSEL-based transmitters.
ECOC
Krzysztof Szczerba, Christoffer Fougstedt, Per Larsson-Edefors, Petter Westbergh, Alexandre Graell i Amat, Lars J. Svensson, Magnus Karlsson, Anders Larsson, Peter A. Andrekson
2015 B conf
Improving Data Access Efficiency by Using Context-Aware Loads and Stores.
LCTES
Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors
2014 J jnl
1.6 GHz Low-Power Cross-Correlator System Enabling Geostationary Earth Orbit Aperture Synthesis.
IEEE J. Solid State Circuits
Erik Ryman, Anders Emrich, Stefan Back Andersson, Lars J. Svensson, Per Larsson-Edefors
2014 — conf
Assessing scrubbing techniques for Xilinx SRAM-based FPGAs in space applications.
FPT
Fredrik Brosser, Emil Milh, Vilhelm Geijer, Per Larsson-Edefors
2014 A conf
Reducing set-associative L1 data cache energy by early load data dependence detection (ELD
DATE
Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors
2014 — conf
Timing- and power-driven ALU design training using spreadsheet-based arithmetic exploration.
EWME
Per Larsson-Edefors, Kjell O. Jeppson
2013 C conf
A SiGe 8-channel comparator for application in a synthetic aperture radiometer.
ISCAS
Erik Ryman, Stefan Back Andersson, J. Riesbeck, Slavko Dejanovic, Anders Emrich, Per Larsson-Edefors
2013 J jnl
Designing a practical data filter cache to improve both energy efficiency and performance.
ACM Trans. Archit. Code Optim.
Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors
2013 — conf
Exploring prefix-tree adders using excel spreadsheets Setting up an explorative learning environment.
MSE
Kjell O. Jeppson, Per Larsson-Edefors
2013 — conf
FlexCore: Implementing an exposed datapath processor.
ICSAMOS
Magnus Själander, Per Larsson-Edefors
2013 A conf
Improving data access efficiency by using a tagless access buffer (TAB).
CGO
Alen Bardizbanyan, Peter Gavin, David B. Whalley, Magnus Själander, Per Larsson-Edefors, Sally A. McKee, Per Stenström
2013 — conf
Manufacturable nanometer designs using standard cells with regular layout.
ISQED
Kasyab P. Subramaniyan, Per Larsson-Edefors
2013 C conf
Speculative tag access for reduced energy dissipation in set-associative L1 data caches.
ICCD
Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors
2012 — conf
Configurable RTL model for level-1 caches.
NORCHIP
Vahid Saljooghi, Alen Bardizbanyan, Magnus Själander, Per Larsson-Edefors
2012 — conf
Data-Width-Driven Power Gating of Integer Arithmetic Circuits.
ISVLSI
Tung Thanh Hoang, Per Larsson-Edefors
2012 C conf
Feasibility study of FPGA-based equalizer for 112-Gbit/s optical fiber receivers.
ISCAS
Fredrik Toft, Niclas Rousk, Jonas Mårtensson, Marco Forzati, Bengt-Erik Olsson, Per Larsson-Edefors
2012 — conf
Viterbi Accelerator for Embedded Processor Datapaths.
ASAP
Muhammad Waqar Azhar, Magnus Själander, Hasan Ali, Akshay Vijayashekar, Tung Thanh Hoang, Kashan Khurshid Ansari, Per Larsson-Edefors
2011 — conf
3.6-GHz 0.2-mW/ch/GHz 65-nm cross-correlator for synthetic aperture radiometry.
CICC
Erik Ryman, Anders Emrich, Stefan Back Andersson, J. Riesbeck, Lars J. Svensson, Per Larsson-Edefors
2011 — conf
Application-Specific Energy Optimization of General-Purpose Datapath Interconnect.
ISVLSI
Babak Hidaji, Salar Alipour, Kasyab P. Subramaniyan, Per Larsson-Edefors
2011 — conf
Reconfigurable Instruction Decoding for a Wide-Control-Word Processor.
IPDPS Workshops
Alen Bardizbanyan, Magnus Själander, Per Larsson-Edefors
2010 J jnl
A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors
2010 C conf
Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor.
DSD
Muhammad Waqar Azhar, Tung Thanh Hoang, Per Larsson-Edefors
2010 — conf
Design space exploration for an embedded processor with flexible datapath interconnect.
ASAP
Tung Thanh Hoang, Ulf Jalmbrant, Erik der Hagopian, Kasyab P. Subramaniyan, Magnus Själander, Per Larsson-Edefors
2010 — conf
Generation and Exploration of Layouts for Area-Efficient Barrel Shifters.
ISVLSI
Alen Bardizbanyan, Kasyab P. Subramaniyan, Per Larsson-Edefors
2010 — conf
On-chip power supply noise and its implications on timing.
ACM Great Lakes Symposium on VLSI
Lars J. Svensson, Johnny Pihl, Daniel A. Andersson, Per Larsson-Edefors
2009 — conf
Custom layout strategy for rectangle-shaped log-depth multiplier reduction tree.
ICECS
Patrik Kimfors, Niklas Broman, Andreas Haraldsson, Kasyab P. Subramaniyan, Magnus Själander, Henrik Eriksson, Per Larsson-Edefors
2009 A conf
Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements.
IPDPS
Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors
2009 J jnl
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing.
J. Signal Process. Syst.
Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström
2009 — conf
High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture.
SoCC
Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors
2009 — conf
Layout exploration of geometrically accurate arithmetic circuits.
ICECS
Kasyab P. Subramaniyan, Emil Axelsson, Per Larsson-Edefors, Mary Sheeran
2009 J jnl
Multiplication Acceleration Through Twin Precision.
IEEE Trans. Very Large Scale Integr. Syst.
Magnus Själander, Per Larsson-Edefors
2009 — conf
Scheduling for an Embedded Architecture with a Flexible Datapath.
ISVLSI
Thomas Schilling, Magnus Själander, Per Larsson-Edefors
2008 — conf
High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree.
ICECS
Magnus Själander, Per Larsson-Edefors
2008 — conf
Noise Interaction Between Power Distribution Grids and Substrate.
ISQED
Daniel A. Andersson, Simon Kristiansson, Lars J. Svensson, Per Larsson-Edefors, Kjell O. Jeppson
2008 — conf
Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach.
ISQED
Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors
2008 J jnl
Time-domain interconnect characterisation flow for appropriate model segmentation.
IET Comput. Digit. Tech.
Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors
2007 — conf
A Flexible Datapath Interconnect for Embedded Applications.
ISVLSI
Magnus Själander, Per Larsson-Edefors, Magnus Björk
2007 — conf
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing.
ICSAMOS
Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström
2007 C conf
High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process.
DSD
Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis
2007 — conf
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays.
ISQED
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson
2007 — conf
Overdrive Power-Gating Techniques for Total Power Minimization.
ISVLSI
Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson
2006 C conf
Multiplier reduction tree with logarithmic logic depth and regular connectivity.
ISCAS
Henrik Eriksson, Per Larsson-Edefors, Mary Sheeran, Magnus Själander, Daniel Johansson, Martin Scholin
2006 — conf
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration.
ISQED
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson
2006 J jnl
Toward architecture-based test-vector generation for timing verification of fast parallel multipliers.
IEEE Trans. Very Large Scale Integr. Syst.
Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert
2005 — conf
A low-leakage twin-precision multiplier using reconfigurable power gating.
ISCAS (2)
Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson
2005 — conf
Accounting for the skin effect during repeater insertion.
ACM Great Lakes Symposium on VLSI
Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors
2004 — conf
A power cut-off technique for gate leakage suppression [CMOS logic circuits].
ESSCIRC
Mindaugas Draidiiulis, Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson
2004 C conf
An Efficient Twin-Precision Multiplier.
ICCD
Magnus Själander, Henrik Eriksson, Per Larsson-Edefors
2004 — conf
Dynamic pass-transistor dot operators for efficient parallel-prefix adders.
ISCAS (2)
Henrik Eriksson, Per Larsson-Edefors
2004 — conf
Evaluation of power cut-off techniques in the presence of gate leakage.
ISCAS (2)
Mindaugas Drazdziulis, Per Larsson-Edefors
2004 — conf
Glitch-conscious low-power design of arithmetic circuits.
ISCAS (2)
Henrik Eriksson, Per Larsson-Edefors
2004 Misc conf
On Maximum Current Estimation in CMOS Digital Circuits.
VLSI Design
Dainius Ciuplys, Per Larsson-Edefors
2004 — conf
On Skin Effect in On-Chip Interconnects.
PATMOS
Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors
2004 — conf
Table-Based Total Power Consumption Estimation of Memory Arrays for Architects.
PATMOS
Minh Quang Do, Per Larsson-Edefors, Lars Bengtsson
2003 C conf
A Mixed-Mode Delay-Locked-Loop Architecture.
ICCD
Daniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors
2003 — conf
A deep submicron power estimation methodology adaptable to variations between power characterization and estimation.
ASP-DAC
Daniel Eckerbert, Per Larsson-Edefors
2003 — conf
A gate leakage reduction strategy for future CMOS circuits.
ESSCIRC
Mindaugas Drazdziulis, Per Larsson-Edefors
2003 — conf
DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures.
Applied Informatics
Minh Quang Do, Lars Bengtsson, Per Larsson-Edefors
2003 — conf
Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects.
ISVLSI
Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars J. Svensson
2003 — conf
Full-custom vs. standard-cell design flow: an adder case study.
ASP-DAC
Henrik Eriksson, Per Larsson-Edefors, Tomas Henriksson, Christer Svensson
2001 — conf
A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder.
ISCAS (4)
Henrik Eriksson, Per Larsson-Edefors, Atila Alvandpour
2001 — conf
A regular parallel multiplier which utilizes multiple carry-propagate adders.
ISCAS (4)
Henrik Eriksson, Per Larsson-Edefors, William P. Marnane
2001 — conf
Cycle-true leakage current modeling for CMOS gates.
ISCAS (5)
Daniel Eckerbert, Per Larsson-Edefors
2001 C conf
Interconnect-Driven Short-Circuit Power Modeling.
DSD
Daniel Eckerbert, Per Larsson-Edefors
2001 — conf
VLSI implementation of CRC-32 for 10 Gigabit Ethernet.
ICECS
Tomas Henriksson, Henrik Eriksson, Ulf Nordqvist, Per Larsson-Edefors, Dake Liu
2000 C conf
An interconnect-driven design of a DFT processor.
ISCAS
Daniel Eckerbert, Henrik Eriksson, Per Larsson-Edefors, Anders Edman
2000 C conf
GLMC: interconnect length estimation by growth-limited multifold clustering.
ISCAS
Atila Alvandpour, Per Larsson-Edefors, Christer Svensson
2000 — conf
Impact of Voltage Scaling on Glitch Power Consumption.
PATMOS
Henrik Eriksson, Per Larsson-Edefors
1999 — conf
A leakage-tolerant multi-phase keeper for wide domino circuits.
ICECS
Atila Alvandpour, Per Larsson-Edefors, Christer Svensson
1998 — conf
A Miniature Serial-Data SIMD Architecture.
EUROMICRO
Per Larsson-Edefors
1998 A conf
Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits.
ISLPED
Atila Alvandpour, Per Larsson-Edefors, Christer Svensson
1996 J jnl
A 965-Mb/s 1.0-μm standard CMOS twin-pipe serial/parallel multiplier.
IEEE J. Solid State Circuits
Per Larsson-Edefors
1996 J jnl
Technology mapping onto very-high-speed standard CMOS hardware.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Per Larsson-Edefors