Peng Huang

36 papers A* 1A 2C 5Journal 17Unranked 11
YearRankTypeTitle / Venue / Authors
2026 J jnl
Instant-CIM: An Instant Neural Radiance Field Computing-In-Memory Architecture for Low-Power and Real-Time AR/VR Rendering.
IEEE Trans. Computers
Lixia Han, Yiyang Chen, Hui Chen, Xueming Fu, Zheng Zhou, Ke Chen, Peng Huang, Yijun Cui, Weiqiang Liu
2025 J jnl
An Efficient Flash-Based Computing-in-Memory (CIM) Demonstration of High-Precision (32-bit) Nonlinear Partial Differential Equation (PDE) Solver With Ultra-High Endurance and Reliability.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yang Feng, Zhaohui Sun, Chengcheng Wang, Xinyi Guo, Junyao Mei, Yueran Qi, Jing Liu, Junyu Zhang, Jixuan Wu, Xuepeng Zhan, Peng Huang, Jiezhi Chen
2025 J jnl
CIMUS: 3D-Stacked Computing-in-Memory Under Image Sensor Architecture for Efficient Machine Vision.
IEEE Trans. Computers
Lixia Han, Yiyang Chen, Siyuan Chen, Haozhang Yang, Ao Shi, Guihai Yu, Jiaqi Li, Zheng Zhou, Yijiao Wang, Yanzhi Wang, Xiaoyan Liu, Jinfeng Kang, Peng Huang
2025 — conf
Investigation on Temperature-Dependent Resistance States of 40nm MLC-RRAM Macro.
IRPS
Haokai Guan, Yulin Feng, Shichao Zhong, Linbo Shan, Kefan Tao, Peng Huang, Zongwei Wang, Lei Sun, Lifeng Liu, Jinfeng Kang, Yimao Cai
2025 J jnl
Mitigating methodology of hardware non-ideal characteristics for non-volatile memory based neural networks.
Sci. China Inf. Sci.
Lixia Han, Peng Huang, Yijiao Wang, Zheng Zhou, Haozhang Yang, Yiyang Chen, Xiaoyan Liu, Jinfeng Kang
2024 J jnl
CoMN: Algorithm-Hardware Co-Design Platform for Nonvolatile Memory-Based Convolutional Neural Network Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lixia Han, Renjie Pan, Zheng Zhou, Hairuo Lu, Yiyang Chen, Haozhang Yang, Peng Huang, Guangyu Sun, Xiaoyan Liu, Jinfeng Kang
2024 C conf
Low Quantization Error Readout Circuit with Fully Charge-Domain Calculation for Computation-in-Memory Deep Neural Network.
ISCAS
Ao Shi, Yizhou Zhang, Lixia Han, Zheng Zhou, Yiyang Chen, Lifeng Liu, Linxiao Shen, Peng Huang, Xiaoyan Liu, Jinfeng Kang
2024 A conf
Pipeline Design of Nonvolatile-based Computing in Memory for Convolutional Neural Networks Inference Accelerators.
DATE
Lixia Han, Peng Huang, Zheng Zhou, Yiyang Chen, Haozhang Yang, Xiaoyan Liu, Jinfeng Kang
2024 J jnl
Specific ADC of NVM-Based Computation-in-Memory for Deep Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ao Shi, Yizhou Zhang, Lixia Han, Zheng Zhou, Yiyang Chen, Haozhang Yang, Lifeng Liu, Linxiao Shen, Xiaoyan Liu, Jinfeng Kang, Peng Huang
2023 J jnl
A 3.3-Mbit/s true random number generator based on resistive random access memory.
Sci. China Inf. Sci.
Shiyue Song, Peng Huang, Wensheng Shen, Lifeng Liu, Jinfeng Kang
2023 A* conf
A Convolution Neural Network Accelerator Design with Weight Mapping and Pipeline Optimization.
DAC
Lixia Han, Peng Huang, Zheng Zhou, Yiyang Chen, Xiaoyan Liu, Jinfeng Kang
2023 J jnl
An ultra-high-density and energy-efficient content addressable memory design based on 3D-NAND flash.
Sci. China Inf. Sci.
Haozhang Yang, Peng Huang, Runze Han, Xiaoyan Liu, Jinfeng Kang
2023 J jnl
Co-optimization strategy between array operation and weight mapping for flash computing arrays to achieve high computing efficiency and accuracy.
Sci. China Inf. Sci.
Guihai Yu, Peng Huang, Runze Han, Lixia Han, Xiaoyan Liu, Jinfeng Kang
2022 J jnl
Efficient Discrete Temporal Coding Spike-Driven In-Memory Computing Macro for Deep Neural Network Based on Nonvolatile Memory.
IEEE Trans. Circuits Syst. I Regul. Pap.
Lixia Han, Peng Huang, Yijiao Wang, Zheng Zhou, Yizhou Zhang, Xiaoyan Liu, Jinfeng Kang
2022 J jnl
Floating Gate Transistor-Based Accurate Digital In-Memory Computing for Deep Neural Networks.
Adv. Intell. Syst.
Runze Han, Peng Huang, Yachen Xiang, Hong Hu, Sheng Lin, Peiyan Dong, Wensheng Shen, Yanzhi Wang, Xiaoyan Liu, Jinfeng Kang
2021 J jnl
Flash Memory Array for Efficient Implementation of Deep Neural Networks.
Adv. Intell. Syst.
Runze Han, Yachen Xiang, Peng Huang, Yihao Shan, Xiaoyan Liu, Jinfeng Kang
2021 — conf
Novel Weight Mapping Method for Reliable NVM based Neural Network.
IRPS
Lixia Han, Yachen Xiang, Peng Huang, Guihai Yu, Runze Han, Xiaoyan Liu, Jinfeng Kang
2019 — conf
3D Vertical RRAM Array and Device Co-design with Physics-based Spice Model.
ASICON
Weiiie Xu, Yudi Zhao, Peng Huang, Xiaoyan Liu, Jinfeng Kang
2019 J jnl
A Novel Convolution Computing Paradigm Based on NOR Flash Array With High Computing Speed and Energy Efficiency.
IEEE Trans. Circuits Syst. I Regul. Pap.
Runze Han, Peng Huang, Yachen Xiang, Chen Liu, Zhen Dong, Zhiqiang Su, Yongbo Liu, Lu Liu, Xiaoyan Liu, Jinfeng Kang
2019 C conf
Analog Deep Neural Network Based on NOR Flash Computing Array for High Speed/Energy Efficiency Computation.
ISCAS
Yachen Xiang, Peng Huang, Zheng Zhou, Runze Han, Yuning Jiang, Q. M. Shu, Zhiqiang Su, Yongbo Liu, Xiaoyan Liu, Jinfeng Kang
2019 J jnl
Circuit design of RRAM-based neuromorphic hardware systems for classification and modified Hebbian learning.
Sci. China Inf. Sci.
Yuning Jiang, Peng Huang, Zheng Zhou, Jinfeng Kang
2019 J jnl
Efficient evaluation model including interconnect resistance effect for large scale RRAM crossbar array matrix computing.
Sci. China Inf. Sci.
Runze Han, Peng Huang, Yudi Zhao, Xiaole Cui, Xiaoyan Liu, Jinfeng Kang
2019 — conf
FNSim: A Device-Circuit-Algorithm Codesigned Simulator for Flash based Neural Network.
ASICON
Min Zhang, Peng Huang, Yizhou Zhang, Yachen Xiang, Runze Han, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang
2019 — conf
Flash-based Computing in-Memory Scheme for IOT.
ASICON
Jinfeng Kang, Peng Huang, Runze Han, Yachen Xiang, Xiaole Cui, Xiaoyan Liu
2019 — conf
Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design.
ASAP
Feng Wang, Guojie Luo, Guangyu Sun, Jiaxi Zhang, Peng Huang, Jinfeng Kang
2018 C conf
A Novel Convolution Computing Paradigm Based on NOR Flash Array with High Computing Speed and Energy Efficient.
ISCAS
Runze Han, Peng Huang, Yachen Xiang, Chen Liu, Zhekang Dong, Zhiqiang Su, Yongbo Liu, L. Liu, Xiaoyan Liu, Jinfeng Kang
2018 J jnl
Design and Hardware Implementation of Neuromorphic Systems With RRAM Synapses and Threshold-Controlled Neurons for Pattern Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuning Jiang, Peng Huang, Dongbin Zhu, Zheng Zhou, Runze Han, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang
2018 — conf
PBTI evaluation of In0.65Ga0.35As/In0.53Ga0.47As nanowire FETs with Al2O3 and LaAlO3 gate dielectrics.
IRPS
Yun Li, K. L. Wang, Shaoyan Di, Peng Huang, Gang Du, Xiao-Yan Liu
2016 J jnl
Device and Circuit Interaction Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays.
CoRR
Haitong Li, Peng Huang, Bin Gao, Xiaoyan Liu, Jinfeng Kang, H.-S. Philip Wong
2016 — conf
Physical understanding and optimization of resistive switching characteristics in oxide-RRAM.
ESSDERC
Jinfeng Kang, Peng Huang, Zhe Chen, Yudi Zhao, Chen Liu, Runze Han, Lifeng Liu, Xiaoyan Liu, Yangyuan Wang, Bin Gao
2015 — conf
Modeling and design optimization of ReRAM.
ASP-DAC
Jinfeng Kang, Haitong Li, Peng Huang, Zhe Chen, Bin Gao, Xiaoyan Liu, Zizhen Jiang, H.-S. Philip Wong
2015 — conf
RRAM based synaptic devices for neuromorphic visual systems.
DSP
Jinfeng Kang, Bin Gao, Peng Huang, Lifeng Liu, Xiaoyan Liu, H. Y. Yu, Shimeng Yu, H.-S. Philip Wong
2015 A conf
Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model.
DATE
Haitong Li, Zizhen Jiang, Peng Huang, Y. Wu, Hong-Yu Chen, Bin Gao, Xiaoyan Liu, Jinfeng Kang, H.-S. Philip Wong
2014 C conf
Design guidelines for 3D RRAM cross-point architecture.
ISCAS
Shimeng Yu, Yexin Deng, Bin Gao, Peng Huang, Bing Chen, Xiaoyan Liu, Jinfeng Kang, Hong-Yu Chen, Zizhen Jiang, H.-S. Philip Wong
2014 — conf
Parameters extraction on HfOX based RRAM.
ESSDERC
Peng Huang, Bing Chen, Haitong Li, Zhe Chen, Bin Gao, Xiaoyan Liu, Jinfeng Kang
2014 C conf
Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture.
ISCAS
Jinfeng Kang, Bin Gao, Bing Chen, Peng Huang, Feifei Zhang, Xiaoyan Liu, Hong-Yu Chen, Zizhen Jiang, H.-S. Philip Wong, Shimeng Yu