Peng Chen - RankMe

17 papers C 1Journal 10Unranked 6

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A High-Linearity 250-MHz Constant-Slope Digital-to-Time Converter. ICECS Peng Chen, Viet Nguyen, Hongtao Huang, Xiongchuan Huang, Feifan Hong, Pingda Guan, Robert Bogdan Staszewski
2023	J	`jnl`	A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit. IEEE J. Solid State Circuits Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen, Gerd Spalink, Ben Eitel, Morteza S. Alavi, Robert Bogdan Staszewski, Masoud Babaie
2023	J	`jnl`	Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion. IEEE Trans. Circuits Syst. I Regul. Pap. Xi Meng, Haoran Li, Peng Chen, Jun Yin, Pui-In Mak, Rui Paulo Martins
2022	—	`conf`	A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs. ISSCC Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen, Gerd Spalink, Ben Eitel, Ken Yamamoto, Robert Bogdan Staszewski, Morteza S. Alavi, Masoud Babaie
2022	J	`jnl`	A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Peng Chen, Xi Meng, Jun Yin, Pui-In Mak, Rui Paulo Martins, Robert Bogdan Staszewski
2022	J	`jnl`	Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Peng Chen, Jun Yin, Feifei Zhang, Pui-In Mak, Rui Paulo Martins, Robert Bogdan Staszewski
2021	J	`jnl`	A 0.7-V Sub-mW Type-II Phase-Tracking Bluetooth Low Energy Receiver in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Suoping Hu, Peng Chen, Philip Quinlan, Robert Bogdan Staszewski
2021	—	`conf`	A Feedforward and Feedback Constant-Slope Digital-to-Time Converter in 28nm CMOS Achieving ≤ 0.12% INL/Range over >100mV Supply Range. VLSI Circuits Peng Chen, Feifei Zhang, Suoping Hu, Robert Bogdan Staszewski
2021	J	`jnl`	A Type-II Phase-Tracking Receiver. IEEE J. Solid State Circuits Suoping Hu, Jianglin Du, Peng Chen, Hieu Minh Nguyen, Philip Quinlan, Teerachot Siriburanon, Robert Bogdan Staszewski
2021	J	`jnl`	An Active-Under-Coil RFDAC With Analog Linear Interpolation in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Feifei Zhang, Peng Chen, Jeffrey S. Walling, Anding Zhu, Robert Bogdan Staszewski
2019	J	`jnl`	A 31-µW, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS. IEEE J. Solid State Circuits Peng Chen, Feifei Zhang, Zhirui Zong, Suoping Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
2019	J	`jnl`	A Low-Noise Fractional- ${N}$ Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications. IEEE J. Solid State Circuits Zhirui Zong, Peng Chen, Robert Bogdan Staszewski
2018	J	`jnl`	An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order ΔΣ Loop. IEEE Trans. Circuits Syst. I Regul. Pap. Peng Chen, Xiongchuan Huang, Yue Chen, Lianbo Wu, Robert Bogdan Staszewski
2017	—	`conf`	A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS. A-SSCC Peng Chen, Feifei Zhang, Zhirui Zong, Hao Zheng, Teerachot Siriburanon, Robert Bogdan Staszewski
2016	—	`conf`	Exponential extended flash time-to-digital converter. EBCCSP Peng Chen, Robert Bogdan Staszewski
2015	—	`conf`	Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs. ESSCIRC Peng Chen, Xiongchuan Huang, Yao-Hong Liu, Ming Ding, Cui Zhou, Ao Ba, Kathleen Philips, Harmke de Groot, Robert Bogdan Staszewski
2015	C	`conf`	Fractional spur suppression in all-digital phase-locked loops. ISCAS Peng Chen, Xiongchuan Huang, Robert Bogdan Staszewski