Pen-Jui Peng

18 papers Journal 6Unranked 12
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver With Time-Interleaved 2-b/3-b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS.
IEEE J. Solid State Circuits
Yen-Po Lin, Pen-Jui Peng, Chun-Chang Lu, Po-Ting Shen, Yun-Cheng Jao, Ping-Hsuan Hsieh
2025 — conf
7.6 A 2.06pJ/b 106.25Gb/s PAM-4 Receiver with 3-Tap FFE and 1-Tap Speculative DFE in 28nm CMOS.
ISSCC
Yen-Po Lin, Yun-Cheng Jao, Wu-Hung Hsieh, Pen-Jui Peng
2024 — conf
7.7 A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS.
ISSCC
Yen-Po Lin, Pen-Jui Peng, Chun-Chang Lu, Po-Ting Shen, Yun-Cheng Jao, Ping-Hsuan Hsieh
2024 — conf
A 39-Gb/s PAM-3 Transmitter and ADC-Based Receiver Chipset in CMOS Technologies.
A-SSCC
Yen-Po Lin, Chun-Chang Lu, Mei-Hsuan Lu, Yueh-Cheng Tsai, Ping-Hsuan Hsieh, Pen-Jui Peng
2022 J jnl
A 12-14.5-GHz 10.2-mW -249-dB FoM Fractional-N Subsampling PLL With a High-Linearity Phase Interpolator in 40-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Yan-Ting Chen, Pen-Jui Peng, Hung-Wen Lin
2022 J jnl
A 56-Gb/s PAM-4 Transmitter/Receiver Chipset With Nonlinear FFE for VCSEL-Based Optical Links in 40-nm CMOS.
IEEE J. Solid State Circuits
Pen-Jui Peng, Po-Lin Lee, Hsiang-En Huang, Wei-Jian Huang, Ming-Wei Lin, Ying-Zong Juang, Sheng-Hsiang Tseng
2022 — conf
Design of ultra-high-speed Transmitters Beyond 100Gb/s in CMOS Technology.
VLSI-DAT
Pen-Jui Peng
2021 J jnl
A 112-Gb/s PAM-4 Voltage-Mode Transmitter With Four-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40-nm CMOS.
IEEE J. Solid State Circuits
Pen-Jui Peng, Yan-Ting Chen, Sheng-Tsung Lai, Hsiang-En Huang
2021 — conf
A 56-Gb/s PAM-4 Optical Transceiver with Nonlinear FFE for VCSEL Driver in 40nm CMOS.
A-SSCC
Pen-Jui Peng, Hsiang-En Huang, Wei-Chien Huang, Po-Lin Lee, Ming-Wei Lin, Ying-Zong Juang, Sheng-Hsiang Tseng
2020 — conf
6.8 A 100Gb/s NRZ Transmitter with 8-Tap FFE Using a 7b DAC in 40nm CMOS.
ISSCC
Pen-Jui Peng, Sheng-Tsung Lai, Wei-Hung Wang, Chiang-Wei Lin, Wei-Chien Huang, Ted Shih
2019 — conf
A 112Gb/s PAM-4 Voltage-Mode Transmitter with 4-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40nm CMOS.
ISSCC
Pen-Jui Peng, Yan-Ting Chen, Sheng-Tsung Lai, Chao-Hsuan Chen, Hsiang-En Huang, Ted Shih
2018 — conf
A 50-Gb/s Quarter-Rate Voltage-Mode Transmitter with Three-Tap FFE in 40-nm CMOS.
ESSCIRC
Pen-Jui Peng, Yan-Ting Chen, Chao-Hsuan Chen, Sheng-Tsung Lai, Hsiang-En Huang, Ho-Hsuan Lu, Tsai-Chin Yu
2017 — conf
6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS.
ISSCC
Pen-Jui Peng, Jeng-Feng Li, Li-Yang Chen, Jri Lee
2015 J jnl
A 94 GHz 3D Image Radar Engine With 4TX/4RX Beamforming Scan Technique in 65 nm CMOS Technology.
IEEE J. Solid State Circuits
Pen-Jui Peng, Pang-Ning Chen, Chiro Kao, Yu-Lun Chen, Jri Lee
2015 — conf
CW/FMCW/pulse radar engines for 24/26GHz multi-standard applications in 65nm CMOS.
A-SSCC
Li-Yang Chen, Pen-Jui Peng, Chiro Kao, Yu-Lun Chen, Jri Lee
2015 J jnl
Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies.
IEEE J. Solid State Circuits
Jri Lee, Ping-Chuan Chiang, Pen-Jui Peng, Li-Yang Chen, Chih-Chi Weng
2014 — conf
A 94GHz duobinary keying wireless transceiver in 65nm CMOS.
VLSIC
Yu-Lun Chen, Chiro Kao, Pen-Jui Peng, Jri Lee
2013 — conf
A 94GHz 3D-image radar engine with 4TX/4RX beamforming scan technique in 65nm CMOS.
ISSCC
Pang-Ning Chen, Pen-Jui Peng, Chiro Kao, Yu-Lun Chen, Jri Lee