Pei-Wen Luo

16 papers A 1Journal 9Unranked 6
YearRankTypeTitle / Venue / Authors
2016 J jnl
On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tao Wang, Chun Zhang, Jinjun Xiong, Pei-Wen Luo, Liang-Chia Cheng, Yiyu Shi
2016 J jnl
Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling.
Integr.
Hui Geng, Jianming Liu, Jinglan Liu, Pei-Wen Luo, Liang-Chia Cheng, Steven L. Grant, Yiyu Shi
2015 — conf
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs.
VLSIC
Pei-Wen Luo, Chi-Kang Chen, Yu-Hui Sung, Wei Wu, Hsiu-Chuan Shih, Chia-Hsin Lee, Kuo-Hua Lee, Ming-Wei Li, Mei-Chiang Lung, Chun-Nan Lu, Yung-Fa Chou, Po-Lin Shih, Chung-Hu Ke, Chun Shiah, Patrick Stolt, Shigeki Tomishima, Ding-Ming Kwai, Bor-Doou Rong, Nicky Lu, Shih-Lien Lu, Cheng-Wen Wu
2015 J jnl
Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs.
ACM Trans. Design Autom. Electr. Syst.
Chien-Chih Huang, Chin-Long Wey, Jwu-E Chen, Pei-Wen Luo
2015 J jnl
Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hui Geng, Jianming Liu, Pei-Wen Luo, Liang-Chia Cheng, Steven L. Grant, Yiyu Shi
2014 J jnl
DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hsiu-Chuan Shih, Pei-Wen Luo, Jen-Chieh Yeh, Shu-Yen Lin, Ding-Ming Kwai, Shih-Lien Lu, Andre Schaefer, Cheng-Wen Wu
2014 A conf
Variation aware optimal threshold voltage computation for on-chip noise sensors.
ICCAD
Tao Wang, Chun Zhang, Jinjun Xiong, Pei-Wen Luo, Liang-Chia Cheng, Yiyu Shi
2013 — conf
Benchmarking for research in power delivery networks of three-dimensional integrated circuits.
ISPD
Pei-Wen Luo, Chun Zhang, Yung-Tai Chang, Liang-Chia Cheng, Hung-Hsie Lee, Bih-Lan Sheu, Yu-Shih Su, Ding-Ming Kwai, Yiyu Shi
2013 J jnl
Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits.
ACM Trans. Design Autom. Electr. Syst.
Chien-Chih Huang, Chin-Long Wey, Jwu-E Chen, Pei-Wen Luo
2012 — conf
Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction.
ASP-DAC
Tao Wang, Pei-Wen Luo, Yu-Shih Su, Liang-Chia Cheng, Ding-Ming Kwai, Yiyu Shi
2012 — conf
Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs).
ISVLSI
Pei-Wen Luo, Tao Wang, Chin-Long Wey, Liang-Chia Cheng, Bih-Lan Sheu, Yiyu Shi
2011 J jnl
Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey
2011 — conf
Yield-award placement optimization for Switched-Capacitor analog integrated circuits.
SoCC
Chien-Chih Huang, Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey
2010 J jnl
Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey
2009 — conf
Yield evaluation of analog placement with arbitrary capacitor ratio.
ISQED
Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey
2008 J jnl
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu