Pavlos M. Mattheakis

14 papers A* 1A 1B 1C 1Misc 1Journal 4Unranked 4

Year	Rank	Type	Title / Venue / Authors
2020	—	`conf`	Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV. ISPD Dimitrios Mangiras, Pavlos M. Mattheakis, Pierre-Olivier Ribet, Giorgos Dimitrakopoulos
2019	J	`jnl`	Timing-Driven and Placement-Aware Multibit Register Composition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery
2017	A*	`conf`	Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation. DAC Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery
2016	—	`conf`	A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors. ACM Great Lakes Symposium on VLSI Anastasios Psarras, Junghee Lee, Pavlos M. Mattheakis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
2016	J	`jnl`	Accelerating Intercommunication in Highly Parallel Systems. ACM Trans. Archit. Code Optim. Nikolaos Tampouratzis, Pavlos M. Mattheakis, Ioannis Papaefstathiou
2015	J	`jnl`	Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan
2015	—	`conf`	Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization. ACM Great Lakes Symposium on VLSI Subhendu Roy, David Z. Pan, Pavlos M. Mattheakis, Peter S. Colyer, Laurent Masse-Navette, Pierre-Olivier Ribet
2014	—	`conf`	Clock tree resynthesis for multi-corner multi-mode timing closure. ISPD Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan
2014	A	`conf`	Hardware primitives for the synthesis of multithreaded elastic systems. DATE Giorgos Dimitrakopoulos, I. Seitanidis, Anastasios Psarras, K. Tsiouris, Pavlos M. Mattheakis, Jordi Cortadella
2013	—	`—`	Logic synthesis of concurrent control specifications Pavlos M. Mattheakis
2013	Misc	`conf`	Polynomial Complexity Asynchronous Control Circuit Synthesis of Concurrent Specifications Based on Burst-Mode FSM Decomposition. VLSI Design Pavlos M. Mattheakis, Christos P. Sotiriou
2013	J	`jnl`	Significantly reducing MPI intercommunication latency and power overhead in both embedded and HPC systems. ACM Trans. Archit. Code Optim. Pavlos M. Mattheakis, Ioannis Papaefstathiou
2012	C	`conf`	A polynomial time flow for implementing free-choice Petri-nets. ICCD Pavlos M. Mattheakis, Christos P. Sotiriou, Peter A. Beerel
2006	B	`conf`	Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed. FPL Evangelia Kassapaki, Pavlos M. Mattheakis, Christos P. Sotiriou