Pavel Kubalík

29 papers A 1C 11Journal 3Unranked 14

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	Quantized Neural Network with Linearly Approximated Functions on Zynq FPGA. MECO Miroslav Skrbek, Pavel Kubalík, Martin Kohlík, Jaroslav Borecký, Robert Hülle
2023	—	`conf`	Evaluation of the Medium-sized Neural Network using Approximative Computations on Zynq FPGA. MECO Miroslav Skrbek, Pavel Kubalík, Martin Kohlík, Jaroslav Borecký, Robert Hülle
2022	—	`conf`	Approximate arithmetic for modern neural networks and FPGAs. MECO Miroslav Skrbek, Pavel Kubalík
2022	—	`conf`	Feasibility of a Neural Network with Linearly Approximated Functions on Zynq FPGA. ICECS 2022 Miroslav Skrbek, Pavel Kubalík
2020	J	`jnl`	An In-Sight Into How Compression Dictionary Architecture Can Affect the Overall Performance in FPGAs. IEEE Access Matej Bartík, Tomás Benes, Pavel Kubalík
2020	—	`conf`	Low Power Wireless Data Transfer for Internet of Things: GSM Network Measuring Results. MECO Vojtech Procházka, Pavel Kubalík, Hana Kubátová
2019	—	`conf`	Design of a High-Throughput Match Search Unit for Lossless Compression Algorithms. CCWC Matej Bartik, Tomás Benes, Pavel Kubalík
2019	—	`conf`	High Throughput and Low Latency LZ4 Compressor on FPGA. ReConFig Tomás Benes, Matej Bartík, Pavel Kubalík
2019	—	`conf`	Ultra High Resolution Jitter Measurement Method for Ethernet Based Networks. CCWC Karel Hynek, Tomás Benes, Matej Bartik, Pavel Kubalík
2018	A	`conf`	Performance Comparison of Multiple Approaches of Status Register for Medium Density Memory Suitable for Implementation of a Lossless Compression Dictionary: (Abstract Only). FPGA Matej Bartík, Sven Ubik, Pavel Kubalík, Tomás Benes
2017	J	`jnl`	Design of a Residue Number System Based Linear System Solver in Hardware. J. Signal Process. Syst. Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický
2016	—	`conf`	A novel and efficient method to initialize FPGA embedded memory content in asymptotically constant time. ReConFig Matej Bartik, Sven Ubik, Pavel Kubalík
2015	—	`conf`	LZ4 compression algorithm on FPGA. ICECS Matej Bartik, Sven Ubik, Pavel Kubalík
2014	—	`conf`	An ASIC linear congruence solver synthesized with three cell libraries. ICECS Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický
2014	—	`conf`	System on chip design of a linear system solver. ISSoC Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický
2013	C	`conf`	Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver. DSD Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický
2012	—	`conf`	Dedicated hardware implementation of a linear congruence solver in FPGA. ICECS Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický
2011	C	`conf`	Fault Models Usability Study for On-line Tested FPGA. DSD Jaroslav Borecký, Martin Kohlík, Pavel Kubalík, Hana Kubátová
2010	C	`conf`	Faults Coverage Improvement Based on Fault Simulation and Partial Duplication. DSD Jaroslav Borecký, Martin Kohlík, Hana Kubátová, Pavel Kubalík
2009	C	`conf`	Reliable Railway Station System Based on Regular Structure Implemented in FPGA. DSD Jaroslav Borecký, Pavel Kubalík, Hana Kubátová
2008	C	`conf`	An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA. DSD Petr Fiser, Pavel Kubalík, Hana Kubátová
2008	J	`jnl`	Dependable design technique for system-on-chip. J. Syst. Archit. Pavel Kubalík, Hana Kubátová
2008	C	`conf`	Experimental SEU Impact on Digital Design Implemented in FPGAs. DSD Jirí Kvasnicka, Pavel Kubalík, Hana Kubátová
2007	C	`conf`	Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System. DDECS Pavel Kubalík, Jirí Kvasnicka, Hana Kubátová
2006	C	`conf`	Dependability Computation for Fault Tolerant Reconfigurable Duplex System. DDECS Pavel Kubalík, Radek Dobias, Hana Kubátová
2006	C	`conf`	Dependable Design for FPGA Based on Duplex System and Reconfiguration. DSD Pavel Kubalík, Radek Dobias, Hana Kubátová
2006	C	`conf`	Fault Tolerant System Design Method Based on Self-Checking Circuits. IOLTS Pavel Kubalík, Petr Fiser, Hana Kubátová
2006	C	`ed.`	Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006 DDECS Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubátová, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jirí Bucek
2005	—	`conf`	Dependability computations for fault-tolerant system based on FPGA. ICECS Radek Dobias, Pavel Kubalík, Hana Kubátová