Pavel Benácek

12 papers A 2B 3C 1Misc 2Journal 1Unranked 3
YearRankTypeTitle / Venue / Authors
2019 — conf
Accelerated DDoS Attacks Mitigation using Programmable Data Plane.
ANCS
Mário Kuka, Kamil Vojanec, Jan Kucera, Pavel Benácek
2019 Misc conf
Scalable P4 Deparser for Speeds Over 100 Gbps.
FCCM
Jakub Cabal, Pavel Benácek, Jana Foltova, Juraj Holub
2018 A conf
Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput.
FPGA
Jakub Cabal, Pavel Benácek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek
2018 — conf
Enhanced Flow Monitoring with P4 Generated Flexible Packet Parser.
AIMS
Tomás Cejka, Petr Velan, Jirí Havránek, Pavel Benácek
2018 J jnl
P4-To-VHDL: Automatic generation of high-speed input and output network blocks.
Microprocess. Microsystems
Pavel Benácek, Viktor Pus, Hana Kubátová, Tomás Cejka
2018 B conf
Verification of Generated RTL from P4 Source Code.
ICNP
Radek Isa, Pavel Benácek, Viktor Pus
2017 B conf
Line rate programmable packet processing in 100Gb networks.
FPL
Pavel Benácek, Viktor Pus, Jan Korenek, Michal Kekely
2016 Misc conf
P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers.
FCCM
Pavel Benácek, Viktor Pus, Hana Kubátová
2014 A conf
Application specific processor with high level synthesized instructions (abstract only).
FPGA
Viktor Pus, Pavel Benácek
2014 C conf
Architecture of Effective High-Speed Network Stream Merger.
DSD
Pavel Benácek, Hana Kubátová, Viktor Pus
2014 — conf
Change-point detection method on 100 Gb/s ethernet interface.
ANCS
Pavel Benácek, Rudolf B. Blazek, Tomás Cejka, Hana Kubátová
2014 B conf
Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring.
FPL
Lukas Kekely, Viktor Pus, Pavel Benácek, Jan Korenek