Pavan Kumar Hanumolu

195 papers A* 2A 2C 2Misc 2Journal 90Unranked 97

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 1.54-pJ/b 64-Gb/s 16-QAM Intradyne Coherent Optical Receiver in 28-nm CMOS. IEEE J. Solid State Circuits Ahmed E. AbdelRahman, Mohamed Badr Younis, Mohamed Osama Selim, Mohamed Saad Aly, Mahmoud A. Khalil, Pavan Kumar Hanumolu
2026	J	`jnl`	A Carrier Phase Recovery Loop for a 3.2-pJ/b, 24-Gb/s QPSK Coherent Optical Receiver. IEEE J. Solid State Circuits Ahmed E. AbdelRahman, Mostafa Gamal Ahmed, Mahmoud A. Khalil, Mohamed Badr Younis, Kyu-Sang Park, Pavan Kumar Hanumolu
2025	—	`conf`	36.7 A 1.54pJ/b 64Gb/s 16-QAM Intradyne Coherent Optical Receiver in 28nm CMOS. ISSCC Ahmed E. AbdelRahman, Mohamed Badr Younis, Mohamed Osama Selim, Mohamed Saad Aly, Mahmoud A. Khalil, Pavan Kumar Hanumolu
2025	J	`jnl`	Compute SNDR-Boosted 22-nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation. IEEE J. Solid State Circuits Saion K. Roy, Han-Mo Ou, Mostafa Gamal Ahmed, Peter Deaville, Bonan Zhang, Naveen Verma, Pavan Kumar Hanumolu, Naresh R. Shanbhag
2025	J	`jnl`	Toward Engineering AGI: Benchmarking the Engineering Design Capabilities of LLMs. CoRR Xingang Guo, Yaxin Li, Xiangyi Kong, Yilan Jiang, Xiayu Zhao, Zhihua Gong, Yufan Zhang, Daixuan Li, Tianle Sang, Beixiao Zhu, Gregory Jun, Yingbing Huang, Yiqi Liu, Yuqi Xue, Rahul Dev Kundu, Qi Jian Lim, Yizhou Zhao, Luke Alexander Granger, Mohamed Badr Younis, Darioush Keivan, Nippun Sabharwal, Shreyanka Sinha, Prakhar Agarwal, Kojo Vandyck, Hanlin Mai, Zichen Wang, Aditya Venkatesh, Ayush Barik, Jiankun Yang, Chongying Yue, Jingjie He, Libin Wang, Licheng Xu, Hao Chen, Jinwen Wang, Liujun Xu, Rushabh Shetty, Ziheng Guo, Dahui Song, Manvi Jha, Weijie Liang, Weiman Yan, Bryan Zhang, Sahil Bhandary Karnoor, Jialiang Zhang, Rutva Pandya, Xinyi Gong, Mithesh Ballae Ganesh, Feize Shi, Ruiling Xu, Yifan Zhang, Yanfeng Ouyang, Lianhui Qin, Elyse Rosenbaum, Corey Snyder, Peter Seiler, Geir E. Dullerud, Xiaojia Shelly Zhang, Zuofu Cheng, Pavan Kumar Hanumolu, Jian Huang, Mayank Kulkarni, Mahdi Namazifar, Huan Zhang, Bin Hu
2024	—	`conf`	7.8 A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and -54.4dBc Spurs Under 50mV Supply Noise. ISSCC Mahmoud A. Khalil, Mohamed Badr Younis, Ruhao Xia, Ahmed E. AbdelRahman, Tianyu Wang, Kyu-Sang Park, Pavan Kumar Hanumolu
2023	—	`conf`	A $1.4\mu$ W/MHz 100MHz RC Oscillator with $\pm$ 1030ppm Inaccuracy from $-40^{\circ}\mathrm{C}$ to $85^{\circ}\mathrm{C}$ After Accelerated Aging for 500 Hours at $125^{\circ}\mathrm{C}$. ISSCC Kyu-Sang Park, Nilanjan Pal, Yongxin Li, Ruhao Xia, Tianyu Wang, Ahmed E. AbdelRahman, Pavan Kumar Hanumolu
2023	J	`jnl`	A 1-μW/MHz RC Oscillator With Three-Point Trimmed 2.1-ppm/°C and Single-Point Trimmed 8.7-ppm/°C Stability From40 °C to 95 °C. IEEE J. Solid State Circuits Kyu-Sang Park, Amr Khashaba, Ahmed E. AbdelRahman, Yongxin Li, Tianyu Wang, Ruhao Xia, Nilanjan Pal, Pavan Kumar Hanumolu
2023	J	`jnl`	A 20-μs Turn-On Time, 24-kHz Resolution, 1.5-100-MHz Digitally Programmable Temperature-Compensated Clock Generator. IEEE J. Solid State Circuits Yongxin Li, Nilanjan Pal, Tianyu Wang, Mostafa Gamal Ahmed, Ahmed E. AbdelRahman, Mohamed Badr Younis, Kyu-Sang Park, Ruhao Xia, Pavan Kumar Hanumolu
2023	—	`conf`	A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop. VLSI Technology and Circuits Mohamed Badr Younis, Mostafa Gamal Ahmed, Tianyu Wang, Ahmed E. AbdelRahman, Mahmoud A. Khalil, Anup P. Jose, Pavan Kumar Hanumolu
2023	—	`conf`	A 7 pA/$\surd\text{Hz}$ Asymmetric Differential TIA for 100Gb/s PAM-4 links with -14dBm Optical Sensitivity in 16nm CMOS. ISSCC Kadaba Lakshmikumar, Alexander Kurylak, Romesh Kumar Nandwana, Bibhu Das, Joe Pampanin, Mike Brubaker, Pavan Kumar Hanumolu
2023	—	`conf`	A Carrier-Phase-Recovery Loop for a 3.2pJ/b 24Gb/s QPSK Coherent Optical Receiver. ISSCC Ahmed E. AbdelRahman, Mostafa Gamal Ahmed, Mahmoud A. Khalil, Mohamed Badr Younis, Kyu-Sang Park, Pavan Kumar Hanumolu
2023	J	`jnl`	A Temperature- and Aging-Compensated RC Oscillator With ±1030-ppm Inaccuracy From40 °C to 85 °C After Accelerated Aging for 500 h at 125 °C. IEEE J. Solid State Circuits Kyu-Sang Park, Nilanjan Pal, Yongxin Li, Ruhao Xia, Tianyu Wang, Ahmed E. AbdelRahman, Pavan Kumar Hanumolu
2023	—	`conf`	Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation. ESSCIRC Saion K. Roy, Han-Mo Ou, Mostafa Gamal Ahmed, Peter Deaville, Bonan Zhang, Naveen Verma, Pavan Kumar Hanumolu, Naresh R. Shanbhag
2022	—	`conf`	A 20µs turn-on time, 24kHz resolution, 1.5-100MHz digitally programmable temperature-compensated clock generator with 7.5ppm/°C inaccuracy. CICC Yongxin Li, Nilanjan Pal, Tianyu Wang, Mostafa Gamal Ahmed, Ahmed E. AbdelRahman, Mohamed Badr Younis, Ruhao Xia, Kyu-Sang Park, Pavan Kumar Hanumolu
2022	J	`jnl`	A 3.2-GHz 405 fs IEEE J. Solid State Circuits Ahmed Elmallah, Junheng Zhu, Amr Khashaba, Karim M. Megawer, Ahmed Elkholy, Pavan Kumar Hanumolu
2022	J	`jnl`	A 32-MHz, 34-μW Temperature-Compensated RC Oscillator Using Pulse Density Modulated Resistors. IEEE J. Solid State Circuits Amr Khashaba, Junheng Zhu, Nilanjan Pal, Mostafa Gamal Ahmed, Pavan Kumar Hanumolu
2022	J	`jnl`	A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process. IEEE J. Solid State Circuits Tianyu Wang, Da Wei, Ranick Ng, Gaurav Malhotra, Anup P. Jose, Amir Amirkhany, Pavan Kumar Hanumolu
2022	J	`jnl`	Guest Editorial Message From the Outgoing Editor-in-Chief. IEEE J. Solid State Circuits Pavan Kumar Hanumolu
2022	—	`conf`	High-Performance CMOS TIA for Data Center Optical Interconnects. BCICTS Kadaba R. Lakshmikumar, Alexander Kurylak, Romesh Kumar Nandwana, Bibhu Das, Joe Pampanin, Vito Boccuzzi, Pavan Kumar Hanumolu
2021	J	`jnl`	A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling. IEEE J. Solid State Circuits Mostafa Gamal Ahmed, Dongwook Kim, Romesh Kumar Nandwana, Ahmed Elkholy, Kadaba R. Lakshmikumar, Pavan Kumar Hanumolu
2021	—	`conf`	A 3.2GHz 405fsrms jitter -237.2dB-FoMJIT ring-based fractional-N synthesizer using two-step quantization noise cancellation and piecewise-linear nonlinearity correction. CICC Ahmed Elmallah, Junheng Zhu, Amr Khashaba, Karim M. Megawer, Ahmed Elkholy, Pavan Kumar Hanumolu
2021	J	`jnl`	A 91.15% Efficient 2.3-5-V Input 10-35-V Output Hybrid Boost Converter for LED-Driver Applications. IEEE J. Solid State Circuits Nilanjan Pal, Adam Fish, William McIntyre, Nathanael Griesert, Greg Winter, Travis Eichhorn, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu
2021	—	`conf`	A second-order temperature compensated 1μW/MHz 100MHz RC oscillator with ±140ppm inaccuracy from -40°C to 95°C. CICC Kyu-Sang Park, Amr Khashaba, Ahmed E. AbdelRahman, Yongxin Li, Tianyu Wang, Ruhao Xia, Nilanjan Pal, Pavan Kumar Hanumolu
2021	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Pavan Kumar Hanumolu
2021	J	`jnl`	New Associate Editors. IEEE J. Solid State Circuits Pavan Kumar Hanumolu
2020	—	`conf`	3.2 A 0.0088mm ISSCC Amr Khashaba, Junheng Zhu, Ahmed Elmallah, Mostafa Gamal Ahmed, Pavan Kumar Hanumolu
2020	—	`conf`	3.5 A 34µW 32MHz RC Oscillator with ±530ppm Inaccuracy from -40°C to 85°C and 80ppm/V Supply Sensitivity Enabled by Pulse-Density Modulated Resistors. ISSCC Amr Khashaba, Junheng Zhu, Mostafa Gamal Ahmed, Nilanjan Pal, Pavan Kumar Hanumolu
2020	J	`jnl`	A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS. IEEE J. Solid State Circuits Dongwook Kim, Mostafa Gamal Ahmed, Woo-Seok Choi, Ahmed Elkholy, Pavan Kumar Hanumolu
2020	—	`conf`	A 91% efficient 30V hybrid boost-SC converter based backlight LED driver in 180nm CMOS. CICC Nilanjan Pal, Adam Fish, William McIntyre, Nathanael Griesert, Greg Winter, Travis Eichhorn, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu
2020	J	`jnl`	A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques. IEEE J. Solid State Circuits Amr Khashaba, Ahmed Elkholy, Karim M. Megawer, Mostafa Gamal Ahmed, Pavan Kumar Hanumolu
2020	J	`jnl`	Hybrid Dickson Switched-Capacitor Converter With Wide Conversion Ratio in 65-nm CMOS. IEEE J. Solid State Circuits Pourya Assem, Wen-Chuen Liu, Yutian Lei, Pavan Kumar Hanumolu, Robert C. N. Pilawa-Podgurski
2020	J	`jnl`	New Associate Editors. IEEE J. Solid State Circuits Pavan Kumar Hanumolu
2019	J	`jnl`	34-GBd Linear Transimpedance Amplifier for 200-Gb/s DP-16-QAM Optical Coherent Receivers. IEEE J. Solid State Circuits Mostafa Gamal Ahmed, Tam N. Huynh, Christopher Williams, Yong Wang, Pavan Kumar Hanumolu, Alexander V. Rylyakov
2019	J	`jnl`	A 0.016 mm IEEE J. Solid State Circuits Junheng Zhu, Woo-Seok Choi, Pavan Kumar Hanumolu
2019	J	`jnl`	A 15-Gb/s Sub-Baud-Rate Digital CDR. IEEE J. Solid State Circuits Dongwook Kim, Woo-Seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar Hanumolu
2019	J	`jnl`	A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler. IEEE J. Solid State Circuits Ahmed Elkholy, Daniel Coombs, Romesh Kumar Nandwana, Ahmed Elmallah, Pavan Kumar Hanumolu
2019	—	`conf`	A 54MHz Crystal Oscillator With 30× 18.5 Start-Up Time Reduction Using 2-Step Injection in 65nm CMOS. ISSCC Karim M. Megawer, Nilanjan Pal, Ahmed Elkholy, Mostafa Gamal Ahmed, Amr Khashaba, Danielle Griffith, Pavan Kumar Hanumolu
2019	—	`conf`	A 5GHz 245fsrms 8mW Ring Oscillator-based Digital Frequency Synthesizer. CICC Amr Khashaba, Ahmed Elkholy, Karim M. Megawer, Mostafa Gamal Ahmed, Pavan Kumar Hanumolu
2019	J	`jnl`	A 6 $\mu$ W ±50 ppm/°C ±1500 ppm/V 1.5 MHz $RC$ Oscillator Using Self-Regulation. IEEE Trans. Circuits Syst. II Express Briefs Tianyu Wang, Danielle Griffith, Mostafa Gamal Ahmed, Junheng Zhu, Da Wei, Ahmed Elkholy, Ahmed Elmallah, Pavan Kumar Hanumolu
2019	J	`jnl`	A Fast Startup CMOS Crystal Oscillator Using Two-Step Injection. IEEE J. Solid State Circuits Karim M. Megawer, Nilanjan Pal, Ahmed Elkholy, Mostafa Gamal Ahmed, Amr Khashaba, Danielle Griffith, Pavan Kumar Hanumolu
2019	J	`jnl`	Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers. IEEE J. Solid State Circuits Karim M. Megawer, Ahmed Elkholy, Mostafa Gamal Ahmed, Ahmed Elmallah, Pavan Kumar Hanumolu
2019	J	`jnl`	Message From the Incoming Editor-in-Chief. IEEE J. Solid State Circuits Pavan Kumar Hanumolu
2019	J	`jnl`	Signal Processing Foundations for Time-Based Signal Representations: Neurobiological parallels to engineered systems designed for energy efficiency or hardware simplicity. IEEE Signal Process. Mag. Noyan Cem Sevüktekin, Lav R. Varshney, Pavan Kumar Hanumolu, Andrew C. Singer
2018	J	`jnl`	A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation. IEEE J. Solid State Circuits Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu
2018	—	`conf`	A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS. CICC Ahmed Elmallah, Mostafa Gamal Ahmed, Ahmed Elkholy, Woo-Seok Choi, Pavan Kumar Hanumolu
2018	J	`jnl`	A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects. IEEE J. Solid State Circuits Da Wei, Tejasvi Anand, Guanghua Shu, José E. Schutt-Ainé, Pavan Kumar Hanumolu
2018	J	`jnl`	A 10-MHz 2-800-mA 0.5-1.5-V 90% Peak Efficiency Time-Based Buck Converter With Seamless Transition Between PWM/PFM Modes. IEEE J. Solid State Circuits Seong Joong Kim, Woo-Seok Choi, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu
2018	J	`jnl`	A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS. IEEE J. Solid State Circuits Mostafa Gamal Ahmed, Mrunmay Talegaonkar, Ahmed Elkholy, Guanghua Shu, Ahmed Elmallah, Alexander V. Rylyakov, Pavan Kumar Hanumolu
2018	—	`conf`	A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR. CICC Dongwook Kim, Woo-Seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar Hanumolu
2018	—	`conf`	A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS. ISSCC Karim M. Megawer, Ahmed Elkholy, Daniel Coombs, Mostafa Gamal Ahmed, Ahmed Elmallah, Pavan Kumar Hanumolu
2018	J	`jnl`	A 6.75-8.25-GHz -250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier. IEEE J. Solid State Circuits Ahmed Elkholy, Ahmed Elmallah, Mostafa Gamal Ahmed, Pavan Kumar Hanumolu
2018	J	`jnl`	A Modulo-Based Architecture for Analog-to-Digital Conversion. CoRR Or Ordentlich, Gizem Tabak, Pavan Kumar Hanumolu, Andrew C. Singer, Gregory W. Wornell
2018	J	`jnl`	A Modulo-Based Architecture for Analog-to-Digital Conversion. IEEE J. Sel. Top. Signal Process. Or Ordentlich, Gizem Tabak, Pavan Kumar Hanumolu, Andrew C. Singer, Gregory W. Wornell
2018	A*	`conf`	Guaranteeing Local Differential Privacy on Ultra-Low-Power Systems. ISCA Woo-Seok Choi, Matthew Tomei, Jose Rodrigo Sanchez Vicarte, Pavan Kumar Hanumolu, Rakesh Kumar
2018	J	`jnl`	Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers. IEEE J. Solid State Circuits Ahmed Elkholy, Saurabh Saxena, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu
2018	—	`conf`	Session 25 overview: Clock generation for high-speed links: Wireline subcommittee. ISSCC Roberto Nonis, Pavan Kumar Hanumolu, Frank O'Mahony
2018	Misc	`conf`	Time-Based PWM Controller for Fully Integrated High Speed Switching DC-DC Converters - An Alternative to Conventional Analog and Digital Controllers. VLSID Qadeer Ahmad Khan, Seong Joong Kim, Pavan Kumar Hanumolu
2017	—	`conf`	10.3 A 94.2%-peak-efficiency 1.53A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65nm CMOS. ISSCC Wen-Chuen Liu, Pourya Assem, Yutian Lei, Pavan Kumar Hanumolu, Robert C. N. Pilawa-Podgurski
2017	—	`conf`	29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS. ISSCC Romesh Kumar Nandwana, Saurabh Saxena, Ahmed Elkholy, Mrunmay Talegaonkar, Junheng Zhu, Woo-Seok Choi, Ahmed Elmallah, Pavan Kumar Hanumolu
2017	—	`conf`	8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS. ISSCC Daniel Coombs, Ahmed Elkholy, Romesh Kumar Nandwana, Ahmed Elmallah, Pavan Kumar Hanumolu
2017	J	`jnl`	A 0.0021 mm IEEE J. Solid State Circuits Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu
2017	—	`conf`	A 0.7V time-based inductor for fully integrated low bandwidth filter applications. CICC Braedon Salz, Mrunmay Talegaonkar, Guanghua Shu, Ahmed Elmallah, Romesh Kumar Nandwana, Bibhudatta Sahoo, Pavan Kumar Hanumolu
2017	J	`jnl`	A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC. IEEE Trans. Circuits Syst. I Regul. Pap. Romesh Kumar Nandwana, Saurabh Saxena, Amr Elshazly, Kartikeya Mayaram, Pavan Kumar Hanumolu
2017	—	`conf`	A 10MHz 2mA-800mA 0.5V-1.5V 90% peak efficiency time-based buck converter with seamless transition between PWM/PFM modes. CICC Seong Joong Kim, Woo-Seok Choi, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu
2017	J	`jnl`	A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver. IEEE J. Solid State Circuits Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Pavan Kumar Hanumolu
2017	—	`conf`	A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS. CICC Junheng Zhu, Makrand Mahalley, Guanghua Shu, Woo-Seok Choi, Romesh Kumar Nandwana, Ahmed Elkholy, Bibhudatta Sahoo, Pavan Kumar Hanumolu
2017	J	`jnl`	A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. IEEE J. Solid State Circuits Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
2017	—	`conf`	EE4: Semiconductor economics: How business decisions are engineered. ISSCC Ichiro Fujimori, Pavan Kumar Hanumolu
2017	—	`conf`	F2: High-performance frequency generation for wireless and wireline systems. ISSCC Jiayoon Ru, Kohei Onizuka, Pavan Kumar Hanumolu, Roberto Nonis, Howard C. Luong, Jan Craninckx
2017	—	`conf`	Time-based ΑΣADCs. CICC Pavan Kumar Hanumolu
2017	A*	`conf`	Understanding and Optimizing Power Consumption in Memory Networks. HPCA Xun Jian, Pavan Kumar Hanumolu, Rakesh Kumar
2016	—	`conf`	10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS. ISSCC Ahmed Elkholy, Ahmed Elmallah, Mohamed Elzeftawi, Ken Chang, Pavan Kumar Hanumolu
2016	—	`conf`	19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS. ISSCC Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu
2016	—	`conf`	23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. ISSCC Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Romesh Kumar Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu
2016	J	`jnl`	A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider. IEEE J. Solid State Circuits Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu
2016	J	`jnl`	A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition. IEEE J. Solid State Circuits Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu
2016	J	`jnl`	A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity. IEEE J. Solid State Circuits Tejasvi Anand, Kofi A. A. Makinwa, Pavan Kumar Hanumolu
2016	—	`conf`	F4: Emerging short-reach and high-density interconnect solutions for internet of everything. ISSCC Ichiro Fujimori, Martin Brox, Elad Alon, Pavan Kumar Hanumolu, Gerrit den Besten, Hideyuki Nosaka
2015	—	`conf`	10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS. ISSCC Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, Pavan Kumar Hanumolu
2015	—	`conf`	12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm ISSCC Seong Joong Kim, Romesh Kumar Nandwana, Qadeer Ahmad Khan, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu
2015	—	`conf`	3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS. ISSCC Tejasvi Anand, Mrunmay Talegaonkar, Ahmed Elkholy, Saurabh Saxena, Amr Elshazly, Pavan Kumar Hanumolu
2015	—	`conf`	3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS. ISSCC Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu
2015	—	`conf`	A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. VLSIC Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Seong Joong Kim, Woo-Seok Choi, Pavan Kumar Hanumolu
2015	J	`jnl`	A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC. IEEE J. Solid State Circuits Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
2015	J	`jnl`	A 4-Phase 30-70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator. IEEE J. Solid State Circuits Seong Joong Kim, Romesh Kumar Nandwana, Qadeer Khan, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu
2015	—	`conf`	A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter. CICC Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu
2015	—	`conf`	A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS. VLSIC Karthikeyan Reddy, Siladitya Dey, Sachin Rao, Brian Young, Praveen Prabha, Pavan Kumar Hanumolu
2015	J	`jnl`	A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links. IEEE J. Solid State Circuits Tejasvi Anand, Mrunmay Talegaonkar, Ahmed Elkholy, Saurabh Saxena, Amr Elshazly, Pavan Kumar Hanumolu
2015	J	`jnl`	A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links. IEEE J. Solid State Circuits Woo-Seok Choi, Tejasvi Anand, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu
2015	J	`jnl`	A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. IEEE J. Solid State Circuits Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
2015	J	`jnl`	A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications. IEEE J. Solid State Circuits Praveen Prabha, Seong Joong Kim, Karthikeyan Reddy, Sachin Rao, Nathanael Griesert, Arun Rao, Greg Winter, Pavan Kumar Hanumolu
2015	—	`conf`	A self-referenced VCO-based temperature sensor with 0.034°C/mV supply sensitivity in 65nm CMOS. VLSIC Tejasvi Anand, Kofi A. A. Makinwa, Pavan Kumar Hanumolu
2015	J	`jnl`	Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers. IEEE J. Solid State Circuits Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, Pavan Kumar Hanumolu
2015	J	`jnl`	High Frequency Buck Converter Design Using Time-Based Control Techniques. IEEE J. Solid State Circuits Seong Joong Kim, Qadeer Khan, Mrunmay Talegaonkar, Amr Elshazly, Arun Rao, Nathanael Griesert, Greg Winter, William McIntyre, Pavan Kumar Hanumolu
2015	—	`conf`	Low dropout regulators. CICC Pavan Kumar Hanumolu
2014	—	`conf`	15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS. ISSCC Ahmed Elkholy, Amr Elshazly, Saurabh Saxena, Guanghua Shu, Pavan Kumar Hanumolu
2014	—	`conf`	8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. ISSCC Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Tejasvi Anand, Amr Elshazly, Pavan Kumar Hanumolu
2014	—	`conf`	A 10-25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW. VLSIC Qadeer Ahmad Khan, Seong Joong Kim, Mrunmay Talegaonkar, Amr Elshazly, Arun Rao, Nathanael Griesert, Greg Winter, William McIntyre, Pavan Kumar Hanumolu
2014	—	`conf`	A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC. VLSIC Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
2014	—	`conf`	A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. VLSIC Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
2014	—	`conf`	A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. VLSIC Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
2014	J	`jnl`	A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis. IEEE J. Solid State Circuits Saurabh Saxena, Romesh Kumar Nandwana, Pavan Kumar Hanumolu
2014	J	`jnl`	A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links. IEEE J. Solid State Circuits Tejasvi Anand, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu
2014	—	`conf`	A 75dB DR 50MHz BW 3 VLSIC Brian Young, Karthik Reddy, Sachin Rao, Amr Elshazly, Tejasvi Anand, Pavan Kumar Hanumolu
2014	J	`jnl`	A Deterministic Digital Background Calibration Technique for VCO-Based ADCs. IEEE J. Solid State Circuits Sachin Rao, Karthikeyan Reddy, Brian Young, Pavan Kumar Hanumolu
2014	J	`jnl`	A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators - Analysis, Design, and Measurement Techniques. IEEE J. Solid State Circuits Amr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu
2014	J	`jnl`	A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop. IEEE J. Solid State Circuits Guanghua Shu, Saurabh Saxena, Woo-Seok Choi, Mrunmay Talegaonkar, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu
2014	—	`conf`	A VCO-based current-to-digital converter for sensor applications. CICC Praveen Prabha, Seong Joong Kim, Karthikeyan Reddy, Sachin Rao, Nathanael Griesert, Arun Rao, Greg Winter, Pavan Kumar Hanumolu
2014	J	`jnl`	An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS. IEEE J. Solid State Circuits Mrunmay Talegaonkar, Amr Elshazly, Karthikeyan Reddy, Praveen Prabha, Tejasvi Anand, Pavan Kumar Hanumolu
2014	J	`jnl`	Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits Makoto Nagata, Lucien J. Breems, Carlo Samori, Sven Mattisson, Pavan Kumar Hanumolu
2013	—	`conf`	A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time. ISSCC Tejasvi Anand, Mrunmay Talegaonkar, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu
2013	—	`conf`	A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter. CICC Saurabh Saxena, Romesh Kumar Nandwana, Pavan Kumar Hanumolu
2013	J	`jnl`	An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW. IEEE J. Solid State Circuits Ramin Zanbaghi, Pavan Kumar Hanumolu, Terri S. Fiez
2013	J	`jnl`	Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops. IEEE J. Solid State Circuits Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu
2012	—	`conf`	A 0.55V 61dB-SNR 67dB-SFDR 7MHz 4 ISSCC Brian Drost, Mrunmay Talegaonkar, Pavan Kumar Hanumolu
2012	—	`conf`	A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity. VLSIC Amr Elshazly, Rajesh Inti, Mrunmay Talegaonkar, Pavan Kumar Hanumolu
2012	—	`conf`	A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC. ISSCC Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu
2012	J	`jnl`	A 12.5-bit 4 MHz 13.8 mW MASH ΔΣ Modulator With Multirated VCO-Based ADC. IEEE Trans. Circuits Syst. I Regul. Pap. Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez
2012	—	`conf`	A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators. ISSCC Amr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu
2012	J	`jnl`	A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer. IEEE J. Solid State Circuits Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu
2012	—	`conf`	A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer. ISSCC Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu
2012	—	`conf`	A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control. VLSIC Qadeer Khan, Amr Elshazly, Sachin Rao, Rajesh Inti, Pavan Kumar Hanumolu
2012	J	`jnl`	Analog Filter Design Using Ring Oscillator Integrators. IEEE J. Solid State Circuits Brian Drost, Mrunmay Talegaonkar, Pavan Kumar Hanumolu
2012	C	`conf`	Calibration technique for SAR analog-to-digital converters. ISCAS Tao Tong, Wenhuan Yu, Pavan Kumar Hanumolu, Gabor C. Temes
2012	J	`jnl`	Rail-to-Rail Input Pipelined ADC Incorporating Multistage Signal Mapping. IEEE Trans. Circuits Syst. II Express Briefs Naga Sasidhar, David Gubbins, Pavan Kumar Hanumolu, Un-Ku Moon
2012	Misc	`conf`	Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques. VLSI Design Pavan Kumar Hanumolu, Un-Ku Moon, Terri S. Fiez
2011	J	`jnl`	A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration. IEEE J. Solid State Circuits Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu
2011	—	`conf`	A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration. ISSCC Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu
2011	J	`jnl`	A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance. IEEE J. Solid State Circuits Rajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu
2011	—	`conf`	A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance. ISSCC Rajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu
2011	J	`jnl`	A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking. IEEE J. Solid State Circuits Wenjing Yin, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu
2011	J	`jnl`	A 1.2-A Buck-Boost LED Driver With On-Chip Error Averaged SenseFET-Based Current Sensing Technique. IEEE J. Solid State Circuits Sachin Rao, Qadeer Khan, Sarvesh Bang, Damian Swank, Arun Rao, William McIntyre, Pavan Kumar Hanumolu
2011	—	`conf`	A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensing. ISSCC Sachin Rao, Qadeer Khan, Sarvesh Bang, Damian Swank, Arun Rao, William McIntyre, Pavan Kumar Hanumolu
2011	—	`conf`	A 3.3V 500mA digital Buck-Boost converter with 92% peak efficiency using constant ON/OFF time delta-sigma fractional-N control. ESSCIRC Qadeer Khan, Sachin Rao, Damian Swank, Arun Rao, William McIntyre, Sarvesh Bang, Pavan Kumar Hanumolu
2011	—	`conf`	A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer. CICC Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez
2011	J	`jnl`	A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery. IEEE J. Solid State Circuits Wenjing Yin, Rajesh Inti, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu
2011	—	`conf`	A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery. ISSCC Wenjing Yin, Rajesh Inti, Amr Elshazly, Pavan Kumar Hanumolu
2011	—	`conf`	A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application. CICC Sanghyeon Lee, Jeongseok Chae, Mitsuru Aniya, Seiji Takeuchi, Koichi Hamashita, Pavan Kumar Hanumolu, Gabor C. Temes
2011	—	`conf`	A high-PSR LDO using a feedforward supply-noise cancellation technique. CICC Bangda Yang, Brian Drost, Sachin Rao, Pavan Kumar Hanumolu
2011	—	`conf`	A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS. ISSCC Rajesh Inti, Amr Elshazly, Brian Young, Wenjing Yin, Marcel A. Kossel, Thomas Toifl, Pavan Kumar Hanumolu
2011	—	`conf`	Area efficient phase calibration of a 1.6 GHz multiphase DLL. CICC Ankur Agrawal, Pavan Kumar Hanumolu, Gu-Yeon Wei
2011	J	`jnl`	Design Techniques for Wideband Discrete-Time Delta-Sigma ADCs With Extra Loop Delay. IEEE Trans. Circuits Syst. I Regul. Pap. Yan Wang, Pavan Kumar Hanumolu, Gabor C. Temes
2011	J	`jnl`	Design-Oriented Analysis of Circuits With Equality Constraints. IEEE Trans. Circuits Syst. I Regul. Pap. Igor Vytyaz, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
2011	—	`conf`	Digital clock and data recovery circuit design: Challenges and tradeoffs. CICC Mrunmay Talegaonkar, Rajesh Inti, Pavan Kumar Hanumolu
2010	—	`conf`	A 1.2A 2MHz tri-mode Buck-Boost LED driver with feed-forward duty cycle correction. CICC Sarvesh Bang, Damian Swank, Arun Rao, William McIntyre, Qadeer Khan, Pavan Kumar Hanumolu
2010	—	`conf`	A 1.6mW 1.6ps-rms-jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS. CICC Wenjing Yin, Rajesh Inti, Pavan Kumar Hanumolu
2010	—	`conf`	A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth. CICC Brian Young, Sunwoo Kwon, Amr Elshazly, Pavan Kumar Hanumolu
2010	—	`conf`	A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer. CICC Jeongseok Chae, Sanghyeon Lee, Mitsuru Aniya, Seiji Takeuchi, Koichi Hamashita, Pavan Kumar Hanumolu, Gabor C. Temes
2010	J	`jnl`	Analysis and Design Techniques for Supply-Noise Mitigation in Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. Abhijith Arakali, Srikanth Gondi, Pavan Kumar Hanumolu
2010	J	`jnl`	Continuous-Time Input Pipeline ADCs. IEEE J. Solid State Circuits David Gubbins, Bumha Lee, Pavan Kumar Hanumolu, Un-Ku Moon
2009	J	`jnl`	A 10 MS/s 11-bit 0.19 mm IEEE J. Solid State Circuits Min-Gyu Kim, Pavan Kumar Hanumolu, Un-Ku Moon
2009	J	`jnl`	A Digital PLL With a Stochastic Time-to-Digital Converter. IEEE Trans. Circuits Syst. I Regul. Pap. Volodymyr Kratyuk, Pavan Kumar Hanumolu, Kerem Ok, Un-Ku Moon, Kartikeya Mayaram
2009	J	`jnl`	A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback. IEEE J. Solid State Circuits Naga Sasidhar, Youn-Jae Kook, Seiji Takeuchi, Koichi Hamashita, Kaoru Takasuka, Pavan Kumar Hanumolu, Un-Ku Moon
2009	—	`conf`	A continuous-time input pipeline ADC with inherent anti-alias filtering. CICC David Gubbins, Sunwoo Kwon, Bumha Lee, Pavan Kumar Hanumolu, Un-Ku Moon
2009	—	`conf`	A multiplexer-based digital passive linear counter (PLINCO). ICECS Skyler Weaver, Benjamin P. Hershberg, Pavan Kumar Hanumolu, Un-Ku Moon
2009	—	`conf`	An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing. CICC Sunwoo Kwon, Pavan Kumar Hanumolu, Sang-Ho Kim, Sung-No Lee, Seung-Bin You, Ho-Jin Park, Jae-Whui Kim, Un-Ku Moon
2009	J	`jnl`	An 8×5 Gb/s Parallel Receiver With Collaborative Timing Recovery. IEEE J. Solid State Circuits Ankur Agrawal, Andrew Liu, Pavan Kumar Hanumolu, Gu-Yeon Wei
2009	J	`jnl`	Automated Design and Optimization of Low-Noise Oscillators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
2009	J	`jnl`	Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture. IEEE J. Solid State Circuits Abhijith Arakali, Srikanth Gondi, Pavan Kumar Hanumolu
2009	J	`jnl`	Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers. IEEE J. Solid State Circuits Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
2009	—	`conf`	Over-sampled data converters. CICC Pavan Kumar Hanumolu, Alessandro Piovaccari
2008	—	`conf`	A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of -28dB. CICC Abhijith Arakali, Srikanth Gondi, Pavan Kumar Hanumolu
2008	J	`jnl`	A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC. IEEE J. Solid State Circuits Min-Gyu Kim, Gil-Cho Ahn, Pavan Kumar Hanumolu, Sanghyeon Lee, Sang-Ho Kim, Seung-Bin You, Jae-Whui Kim, Gabor C. Temes, Un-Ku Moon
2008	—	`conf`	A 1V downconversion filter using duty-cycle controlled bandwidth tuning. CICC Peter Kurahashi, Pavan Kumar Hanumolu, Un-Ku Moon
2008	—	`conf`	A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction. CICC Ankur Agrawal, Pavan Kumar Hanumolu, Gu-Yeon Wei
2008	J	`jnl`	A Sub-Picosecond Resolution 0.5-1.5 GHz Digital-to-Phase Converter. IEEE J. Solid State Circuits Pavan Kumar Hanumolu, Volodymyr Kratyuk, Gu-Yeon Wei, Un-Ku Moon
2008	J	`jnl`	A Wide-Tracking Range Clock and Data Recovery Circuit. IEEE J. Solid State Circuits Pavan Kumar Hanumolu, Gu-Yeon Wei, Un-Ku Moon
2008	—	`conf`	A continuous-time input pipeline ADC. CICC David Gubbins, Bumha Lee, Pavan Kumar Hanumolu, Un-Ku Moon
2008	—	`conf`	An 8×3.2Gb/s Parallel Receiver with Collaborative Timing Recovery. ISSCC Ankur Agrawal, Pavan Kumar Hanumolu, Gu-Yeon Wei
2008	—	`conf`	Noise tolerant oscillator design using perturbation projection vector analysis. CICC Igor Vytyaz, Josh Carnes, Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
2008	A	`conf`	Periodic Steady-State Analysis Augmented with Design Equality Constraints. DATE Igor Vytyaz, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
2008	J	`jnl`	Sensitivity Analysis for Oscillators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
2008	—	`conf`	Supply-noise mitigation techniques in phase-locked loops. ESSCIRC Abhijith Arakali, Nema Talebbeydokthi, Srikanth Gondi, Pavan Kumar Hanumolu
2007	—	`conf`	A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range. CICC Volodymyr Kratyuk, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
2007	—	`conf`	A 1V 10b 30MSPS Switched-RC Pipelined ADC. CICC Gil-Cho Ahn, Min-Gyu Kim, Pavan Kumar Hanumolu, Un-Ku Moon
2007	—	`conf`	A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance. CICC Merrick Brownlee, Pavan Kumar Hanumolu, Un-Ku Moon
2007	—	`conf`	A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop. CICC Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
2007	J	`jnl`	A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy. IEEE Trans. Circuits Syst. II Express Briefs Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
2007	—	`conf`	Design and Analysis of Noise Tolerant Ring Oscillators Using Maneatis Delay Cells. ICECS Josh Carnes, Igor Vytyaz, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
2007	J	`jnl`	Design of Low-Voltage Highly Linear Switched-R-MOSFET-C Filters. IEEE J. Solid State Circuits Peter Kurahashi, Pavan Kumar Hanumolu, Gabor C. Temes, Un-Ku Moon
2007	—	`conf`	Digitally-Enhanced Phase-Locking Circuits. CICC Pavan Kumar Hanumolu, Gu-Yeon Wei, Un-Ku Moon, Kartikeya Mayaram
2007	A	`conf`	Sensitivity analysis for oscillators. ICCAD Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
2006	—	`conf`	A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning. ISSCC Merrick Brownlee, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
2006	J	`jnl`	A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning. IEEE J. Solid State Circuits Merrick Brownlee, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
2006	—	`conf`	A 0.6V Highly Linear Switched-R-MOSFET-C Filter. CICC Peter Kurahashi, Pavan Kumar Hanumolu, Gabor C. Temes, Un-Ku Moon
2006	—	`conf`	A 1.6Gbps Digital Clock and Data Recovery Circuit. CICC Pavan Kumar Hanumolu, Min-Gyu Kim, Gu-Yeon Wei, Un-Ku Moon
2006	C	`conf`	Constant transconductance bias circuit with an on-chip resistor. ISCAS Nasser Talebbeydokhti, Pavan Kumar Hanumolu, Peter Kurahashi, Un-Ku Moon
2005	J	`jnl`	A 0.8-V accurately tuned linear continuous-time filter. IEEE J. Solid State Circuits Gowtham Vemulapalli, Pavan Kumar Hanumolu, Youn-Jae Kook, Un-Ku Moon
2005	—	`conf`	A low spur fractional-N frequency synthesizer architecture. ISCAS (3) Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
2005	—	`conf`	An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications. ISCAS (4) Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
2004	—	`conf`	A 0.8V accurately-tuned continuous-time filter. CICC Gowtham Vemulapalli, Pavan Kumar Hanumolu, Un-Ku Moon
2004	J	`jnl`	Analysis of charge-pump phase-locked loops. IEEE Trans. Circuits Syst. I Regul. Pap. Pavan Kumar Hanumolu, Merrick Brownlee, Kartikeya Mayaram, Un-Ku Moon
2004	—	`conf`	Jitter in high-speed serial and parallel links. ISCAS (4) Pavan Kumar Hanumolu, Bryan Casper, Randy Mooney, Gu-Yeon Wei, Un-Ku Moon
2003	J	`jnl`	Analysis of PLL clock jitter in high-speed serial links. IEEE Trans. Circuits Syst. II Express Briefs Pavan Kumar Hanumolu, Bryan Casper, Randy Mooney, Gu-Yeon Wei, Un-Ku Moon