Paulo F. Butzen

70 papers A 3C 5Journal 17Unranked 45

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Fast Statistical Estimation of Circuit-Level Cross Section Considering Logical Masking Effects. LATS Clayton R. Farias, Tiago R. Balen, Paulo F. Butzen
2026	—	`conf`	Mitigation of SETs Under Process Variability Effects: Circuit-Level Strategies for Reliable Design. LATS Marina Longo Dias, Bernardo Borges Sandoval, Paulo F. Butzen, Ricardo A. L. Reis, Cristina Meinhardt
2026	—	`conf`	RISC-V Area-Optimized ASIC Design with a Multi-Height 7nm FinFET Standard Cell Library. LASCAS Matheus Lemos, Clayton R. Farias, Paulo F. Butzen, José Rodrigo Azambuja
2025	—	`conf`	Approximate Adders for Efficient Circuits: Advantages and Limitations Compared to RCA. SBCCI Vítor De M. Mandowski, Pedro T. L. Pereira, Paulo F. Butzen, Sergio Bampi, Leomar Soares da Rosa Júnior
2025	J	`jnl`	Efficient Memristive Stateful Logic Exploring Boolean Expressions in the Sum-of-Products Form. IEEE Trans. Circuits Syst. I Regul. Pap. Cesar de S. Dias, Helisa S. de Lima, Raphael Martins Brum, Paulo F. Butzen
2025	—	`conf`	Impact of Circuit-Level Radiation-Hardening Techniques in Adders on a RISC-V Design. SBCCI Marina Longo Dias, Paulo F. Butzen, Ricardo Reis, Cristina Meinhardt
2025	—	`conf`	Improving Circuit Area with a 7Nm Predictive FinFET PDK Multi-Height Standard Cell Library. LASCAS Matheus Lemos, Clayton R. Farias, Paulo F. Butzen, José Rodrigo Azambuja
2025	J	`jnl`	Placement Refinement Strategies for Security Closure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Marcelo Danigno, Mateus Fogaça, Rafael B. Schvittz, Paulo F. Butzen
2025	—	`conf`	Single-Pass Critical Input Vectors Detection. LASCAS João Machado, Matheus F. Pontes, Paulo Flores, Paulo F. Butzen, Leomar Soares da Rosa Júnior
2024	—	`conf`	Cross-Section Estimation for Assessment of Circuit Susceptibility to Radiation. LATS Clayton R. Farias, Tiago R. Balen, Paulo F. Butzen
2024	—	`conf`	Extending Multilevel ALS to Design ATMRs. LASCAS Gabriel Ammes, Guilherme B. Manske, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
2024	—	`conf`	Transistor-Level Logic Gates Ranking Strategy for Selective Hardening. SBESC Glória D. Claro da Silva, Rafael B. Schvittz, Paulo F. Butzen
2023	—	`conf`	A Detailed Electrical Analysis of SEE on 28 nm FDSOI SRAM Architectures. SBCCI Cleiton Magano Marques, Leonardo Heitich Brendler, Frédéric Wrobel, Alexandra L. Zimpeck, Walter E. Calienes Bartra, Paulo F. Butzen, Cristina Meinhardt
2023	—	`conf`	ATMR design by construction based on two-level ALS. SBCCI Gabriel Ammes, Guilherme B. Manske, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
2023	C	`conf`	An Improved method to join BDDs for incompletely specified Boolean functions. ISCAS Renato D. Peralta, Joao P. Nespolo, Paulo F. Butzen, Mariana Kolberg, André Inácio Reis
2023	—	`conf`	Effect of Unique Table Implementation in the Performance of BDD Packages. SBCCI Joao P. Nespolo, Renato D. Peralta, Paulo F. Butzen, André Inácio Reis
2023	J	`jnl`	Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems. J. Electron. Test. Tiago R. Balen, Carlos J. González, Ingrid F. V. Oliveira, Leomar S. da Rosa Jr., Rafael Iankowski Soares, Rafael B. Schvittz, Nemitala Added, Eduardo L. A. Macchione, Vitor A. P. Aguiar, Marcilei Aparecida Guazzelli, Nilberto H. Medina, Paulo F. Butzen
2023	—	`conf`	Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis. ISVLSI Gabriel Ammes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
2022	—	`conf`	A Fast Approximate Function Generation Method to ATMR Architecture. LASCAS Guilherme B. Manske, Clayton R. Farias, Paulo F. Butzen, Leomar S. da Rosa
2022	J	`jnl`	A Predictive Approach for Conditional Execution of Memristive Material Implication Stateful Logic Operations. IEEE J. Emerg. Sel. Topics Circuits Syst. Cesar de S. Dias, Felipe S. Marranghello, Raphael Martins Brum, Paulo F. Butzen
2022	J	`jnl`	A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gabriel Ammes, Walter Lau Neto, Paulo F. Butzen, Pierre-Emmanuel Gaillardon, Renato P. Ribas
2022	—	`conf`	Evaluating Soft Error Reliability of Combinational Circuits Using a Monte Carlo Based Method. LATS Clayton R. Farias, Rafael B. Schvittz, Tiago R. Balen, Paulo F. Butzen
2022	C	`conf`	Fault Tolerance Evaluation of Different Majority Voter Designs. ISCAS Ingrid F. V. Oliveira, Matheus F. Pontes, Rafael B. Schvittz, Leomar S. da Rosa Jr., Paulo F. Butzen, Rafael Iankowski Soares
2022	J	`jnl`	Optimizing machine learning logic circuits with constant signal propagation. Integr. Augusto Andre Souza Berndt, Cristina Meinhardt, André Inácio Reis, Paulo F. Butzen
2022	—	`conf`	Possible Reductions to Generate circuits from BDDs. ISVLSI Eduarde D. Brandão, Joao P. Nespolo, Renato D. Peralta, Paulo F. Butzen, André Inácio Reis
2022	C	`conf`	The Impact of Logic Gates Susceptibility in Overall Circuit Reliability Analysis. ISCAS Matheus F. Pontes, Ingrid F. V. Oliveira, Rafael B. Schvittz, Leomar Soares da Rosa Júnior, Paulo F. Butzen
2021	J	`jnl`	A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. CoRR Gabriel Ammes, Walter Lau Neto, Paulo F. Butzen, Pierre-Emmanuel Gaillardon, Renato P. Ribas
2021	—	`conf`	Benchmarking Open Access VLSI Partitioning Tools. LASCAS Isadora Oliveira, Marcelo Danigno, Paulo F. Butzen, Ricardo Reis
2021	A	`conf`	Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
2021	—	`conf`	Reliability Evaluation of Voters for Fault Tolerant Approximate Systems. LATS Tiago R. Balen, Carlos J. González, Ingrid F. V. Oliveira, Rafael B. Schvittz, Nemitala Added, Eduardo L. A. Macchione, Vitor A. P. de Aguiar, Marcilei Aparecida Guazzelli, Nilberto H. Medina, Paulo F. Butzen
2021	—	`conf`	Soft Error Sensibility Window at FinFET DICE SRAM. LASCAS Maria Eduarda de Melo Hang, Cleiton Magano Marques, Paulo F. Butzen, Cristina Meinhardt
2020	A	`conf`	Contributions to OpenROAD from Abroad: Experiences and Learnings : Invited Paper. ICCAD Mateus Fogaça, Eder Monteiro, Marcelo Danigno, Isadora Oliveira, Paulo F. Butzen, Ricardo Reis
2020	J	`jnl`	Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
2020	A	`conf`	Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients. ITC Rafael B. Schvittz, Paulo F. Butzen, Leomar S. da Rosa
2020	—	`conf`	Soft Error Reliability of SRAM cells during the three operation states. LATS Cleiton Magano Marques, Cristina Meinhardt, Paulo F. Butzen
2019	—	`conf`	An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults. VLSI-SoC (Selected Papers) Rafael B. Schvittz, Denis Teixeira Franco, Leomar S. da Rosa, Paulo F. Butzen
2019	—	`conf`	FBM: A Simple and Fast Algorithm for Placement Legalization. ICECS Jorge Ferreira, Paulo F. Butzen, Cristina Meinhardt, Ricardo A. L. Reis
2019	—	`conf`	Proposal and Evaluation of Pin Access Algorithms for Detailed Routing. ICECS Marcelo Danigno, Paulo F. Butzen, Jorge Ferreira, André Oliveira, Eder Monteiro, Mateus Fogaça, Ricardo Augusto da Luz Reis
2018	—	`conf`	16NM 6T and 8T CMOS SRAM Cell Robustness Against Process Variability and Aging Effects. SBCCI Roberto B. Almeida, Paulo F. Butzen, Cristina Meinhardt
2018	—	`conf`	A Novel SPICE Model of Memristive Devices with Threshold Current Based Control. SBCCI Cesar de S. Dias, Paulo F. Butzen
2018	J	`jnl`	Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies. Microelectron. Reliab. Roberto B. Almeida, Cleiton Magano Marques, Paulo F. Butzen, Fábio G. R. G. da Silva, Ricardo A. L. Reis, Cristina Meinhardt
2018	—	`conf`	Fault masking ratio analysis of majority voters topologies. LATS Ingrid F. V. Oliveira, Rafael B. Schvittz, Paulo F. Butzen
2018	—	`conf`	Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults. ICECS Rafael B. Schvittz, Denis Teixeira Franco, Leomar S. da Rosa Jr., Paulo F. Butzen
2018	—	`conf`	Reliability evaluation of circuits designed in multi- and single-stage versions. LASCAS Rafael B. Schvittz, Matheus F. Pontes, Cristina Meinhardt, Denis Teixeira Franco, Lirida A. B. Naviner, Leomar S. da Rosa, Paulo F. Butzen
2018	—	`conf`	The Suitability of the SPR-MP Method to Evaluate the Reliability of Logic Circuits. ICECS Matheus F. Pontes, Paulo F. Butzen, Rafael B. Schvittz, Leomar S. da Rosa Jr., Denis Teixeira Franco
2017	—	`conf`	Exploring BDDs to reduce test pattern set. LATS Gabriel S. Porto, Paulo F. Butzen, Denis Teixeira Franco
2016	—	`conf`	A probabilistic model for stuck-on faults in combinational logic gates. LATS Rafael B. Schivittz, Denis Teixeira Franco, Cristina Meinhardt, Paulo F. Butzen
2016	—	`conf`	Inserting permanent fault input dependence on PTM to improve robustness evaluation. SBCCI Rafael B. Schivittz, Rafael Fritz, Denis Teixeira Franco, Lirida A. B. Naviner, Cristina Meinhardt, Paulo F. Butzen
2016	—	`conf`	PVT variability analysis of FinFET and CMOS XOR circuits at 16nm. ICECS Fábio G. R. G. da Silva, Paulo F. Butzen, Cristina Meinhardt
2016	J	`jnl`	Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters. Microelectron. Reliab. Mariem Slimani, Paulo F. Butzen, Lirida A. B. Naviner, You Wang, Hao Cai
2016	—	`conf`	Reliability analysis of majority voters under permanent faults. LATS Eduardo Liebl, Cristina Meinhardt, Paulo F. Butzen
2015	C	`conf`	An Incremental Timing-Driven flow using quadratic formulation for detailed placement. VLSI-SoC Guilherme Flach, Jucemar Monteiro, Mateus Fogaça, Julia Casarin Puget, Paulo F. Butzen, Marcelo O. Johann, Ricardo Augusto da Luz Reis
2015	—	`conf`	An evaluation of BTI degradation of 32nm standard cells. ICECS Rafael B. Schivittz, Cristina Meinhardt, Paulo F. Butzen
2015	—	`conf`	Automatic circuit generation for sequential logic debug. ICECS Helder H. Avelar, Paulo F. Butzen, Renato P. Ribas
2013	—	`conf`	A methodology to evaluate the aging impact on flip-flops performance. SBCCI Cicero Nunes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
2013	J	`jnl`	BTI and HCI first-order aging estimation for early use in standard cell technology mapping. Microelectron. Reliab. Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
2013	J	`jnl`	BTI, HCI and TDDB aging impact in flip-flops. Microelectron. Reliab. Cicero Nunes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
2012	J	`jnl`	Design of CMOS logic gates with enhanced robustness against aging degradation. Microelectron. Reliab. Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
2011	J	`jnl`	An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization. IEEE Trans. Very Large Scale Integr. Syst. John Keane, Shrinivas Venkatraman, Paulo F. Butzen, Chris H. Kim
2011	—	`conf`	Area impact analysis of via-configurable regular fabric for digital integrated circuit design. SBCCI Vinícius Dal Bem, Paulo F. Butzen, Carlos Eduardo Klock, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
2011	C	`conf`	Impact and optimization of lithography-aware regular layout in digital circuit design. ICCD Vinícius Dal Bem, Paulo F. Butzen, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
2010	J	`jnl`	Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits. J. Low Power Electron. Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
2010	J	`jnl`	Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits. Microelectron. J. Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, André Inácio Reis, Renato P. Ribas
2010	J	`jnl`	Transistor network restructuring against NBTI degradation. Microelectron. Reliab. Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
2009	—	`conf`	Routing Resistance Influence in Loading Effect on Leakage Analysis. PATMOS Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
2008	—	`conf`	An array-based test circuit for fully automated gate dielectric breakdown characterization. CICC John Keane, Shrinivas Venkatraman, Paulo F. Butzen, Chris H. Kim
2008	—	`conf`	Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms. ACM Great Lakes Symposium on VLSI Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas
2007	—	`conf`	Modeling Subthreshold Leakage Current in General Transistor Networks. ISVLSI Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
2007	—	`conf`	Modeling and estimating leakage current in series-parallel CMOS networks. ACM Great Lakes Symposium on VLSI Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
2007	—	`conf`	Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates. PATMOS Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas