Paulino Ruiz-de-Clavijo

26 papers A 1C 2Journal 8Unranked 15

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	Address-encoded byte order. Microprocess. Microsystems David Guerrero Martos, German Cano-Quiveu, Jorge Juan-Chico, Alejandro Millán, Manuel J. Bellido, Julian Viejo, Paulino Ruiz-de-Clavijo, Enrique Ostúa
2020	J	`jnl`	Using the complement of the cosine to compute trigonometric functions. EURASIP J. Adv. Signal Process. David Guerrero Martos, Alejandro Millán Calderón, Jorge Juan-Chico, Julian Viejo, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa
2018	—	`conf`	A Proposal for a New Way of Classifying Network Security Metrics: Study of the Information Collected through a Honeypot. QRS Companion Alejandro Carrasco, Jorge Ropero, Paulino Ruiz-de-Clavijo, Jaime Benjumea, Amalia Luque
2017	J	`jnl`	Minimalistic SDHC-SPI hardware reader module for boot loader applications. Microelectron. J. Paulino Ruiz-de-Clavijo, Enrique Ostúa, Manuel Jesús Bellido Díaz, Jorge Juan, Julian Viejo, David Guerrero Martos
2011	J	`jnl`	Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation. IEEE Trans. Instrum. Meas. Julian Viejo, Jorge Juan, Manuel Jesús Bellido Díaz, Alejandro Millán, Paulino Ruiz-de-Clavijo
2011	J	`jnl`	Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells. J. Low Power Electron. David Guerrero Martos, Alejandro Millán, Jorge Juan, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo
2010	J	`jnl`	Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies. J. Low Power Electron. Alejandro Millán, Manuel J. Bellido, Jorge Juan, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Julian Viejo
2008	—	`conf`	Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. PATMOS Alejandro Millán, Jorge Juan, Manuel J. Bellido, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Julian Viejo
2007	—	`conf`	Design of a FFT/IFFT module as an IP core suitable for embedded systems. SIES Julian Viejo, Alejandro Millán, Manuel J. Bellido, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Alejandro Muñoz
2007	J	`jnl`	Improving the Performance of Static CMOS Gates by Using Independent Bodies. J. Low Power Electron. David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo
2007	—	`conf`	Static Power Consumption in CMOS Gates Using Independent Bodies. PATMOS David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo
2006	J	`jnl`	Accurate Logic-Level Current Estimation for Digital CMOS Circuits. J. Low Power Electron. Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero Martos, Enrique Ostúa, Julian Viejo
2006	C	`conf`	Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements. IES Julian Viejo, Manuel J. Bellido, Alejandro Millán, Enrique Ostúa, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos
2005	—	`conf`	Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. PATMOS Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Julian Viejo
2005	—	`conf`	Logic-Level Fast Current Simulation for Digital CMOS Circuits. PATMOS Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, Julian Viejo
2004	—	`conf`	Signal Sampling Based Transition Modeling for Digital Gates Characterization. PATMOS Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa
2003	—	`conf`	Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. PATMOS David Guerrero Martos, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán
2003	—	`conf`	Internode: Internal Node Logic Computational Model. Annual Simulation Symposium Alejandro Millán, Manuel J. Bellido, Jorge Juan-Chico, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Enrique Ostúa
2002	—	`conf`	Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). PATMOS Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos
2002	—	`conf`	Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. PATMOS Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Alejandro Millán, David Guerrero Martos
2002	—	`conf`	Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. PATMOS Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos Jesús Jiménez-Fernández, Manuel Valencia
2001	—	`conf`	AUTODDM: automatic characterization tool for the delay degradation model. ICECS Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carmen Baena Oliva, Manuel Valencia
2001	—	`conf`	Gate-level simulation of CMOS circuits using the IDDM model. ISCAS (5) Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero
2001	A	`conf`	HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. DATE Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia-Barrero
2000	—	`conf`	Degradation Delay Model Extension to CMOS Gates. PATMOS Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero
2000	C	`conf`	Inertial and degradation delay model for CMOS logic gates. ISCAS Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia