Paul Villarrubia

20 papers A* 4A 4C 2Journal 3Unranked 7
YearRankTypeTitle / Venue / Authors
2007 — conf
Fast Electrical Correction Using Resizing and Buffering.
ASP-DAC
Shrirang K. Karandikar, Charles J. Alpert, Mehmet Can Yildiz, Paul Villarrubia, Stephen T. Quay, T. Mahmud
2007 A* conf
RQL: Global Placement via Relaxed Quadratic Spreading and Linearization.
DAC
Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu
2006 J jnl
A Fast Hierarchical Quadratic Placement Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng
2005 — conf
A semi-persistent clustering technique for VLSI circuit placement.
ISPD
Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia
2005 A* conf
Diffusion-based placement migration.
DAC
Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia
2005 — conf
Physical design tools for hierarchy.
ISPD
Paul Villarrubia
2005 — conf
The ISPD2005 placement contest and benchmark suite.
ISPD
Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz
2004 J jnl
Benchmarking for large-scale placement and beyond.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden
2004 A conf
True crosstalk aware incremental placement with noise map.
ICCAD
Haoxing Ren, David Zhigang Pan, Paul Villarrubia
2003 J jnl
A practical methodology for early buffer and wire resource allocation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
2003 — conf
Benchmarking for large-scale placement and beyond.
ISPD
Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden
2003 — conf
Important placement considerations for modern VLSI chips.
ISPD
Paul Villarrubia
2003 A conf
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis.
ICCAD
Saurabh N. Adya, Igor L. Markov, Paul Villarrubia
2002 A conf
Free space management for cut-based placement.
ICCAD
Charles J. Alpert, Gi-Joon Nam, Paul Villarrubia
2001 A* conf
A Practical Methodology for Early Buffer and Wire Resource Allocation.
DAC
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
2001 — conf
Buffered Steiner trees for difficult instances.
ISPD
Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia
2000 A* conf
"Timing closure by design, " a high frequency microprocessor design methodology.
DAC
Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia
2000 A conf
Transformational Placement and Synthesis.
DATE
Wilm E. Donath, Prabhakar Kudva, Leon Stok, Paul Villarrubia, Lakshmi N. Reddy, Andrew Sullivan, Kanad Chakraborty
1997 C conf
An Integrated Placement and Synthesis Approach for Timing Closure of PowerPC Microprocessors.
ICCD
Shervin Hojat, Paul Villarrubia
1989 C conf
IBM RISC chip design methodology.
ICCD
Paul Villarrubia, Gary Nusbaum, Robert Masleid, P. T. Patel