Paul T. Hulina

26 papers A* 3B 2C 3Journal 9Unranked 9
YearRankTypeTitle / Venue / Authors
1999 C conf
A Rapid Prototyping Methodology for Reverse Engineering of Legacy Electronic Systems.
IEEE International Workshop on Rapid System Prototyping
Scott Deno, David L. Landis, Paul T. Hulina, Sanjay Balasubramanian
1999 — conf
Computing in Memory Architectures for Digital Image Processing.
MTDT
Luke Roth, Lee D. Coraor, David L. Landis, Paul T. Hulina, Scott Deno
1999 C conf
Evaluation of Computing in Memory Architectures for Digital Image Processing Applications.
ICCD
David L. Landis, Paul T. Hulina, Scott Deno, Luke Roth, Lee D. Coraor
1999 C conf
Language-Based Rapid Prototyping Methods for Legacy System Re-Engineering and Re-Use.
IEEE International Workshop on Rapid System Prototyping
David L. Landis, Praveen Guddeti, Paul T. Hulina, Lee D. Coraor
1997 — conf
A WWW facilitated rapid system prototyping class.
MSE
David L. Landis, Paul T. Hulina
1997 — conf
An electronics manufacturing minor in engineering with emphasis on rapid prototyping.
MSE
Paul T. Hulina, David L. Landis
1995 — conf
A comparative evaluation of software techniques to hide memory latency.
HICSS (1)
Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor
1995 A* conf
Program Balance and Its Impact on High Performance RISC Architectures.
HPCA
Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor
1994 J jnl
Memory Latency Effects in Decoupled Architectures.
IEEE Trans. Computers
Lizyamma Kurian, Paul T. Hulina, Lee D. Coraor
1994 — conf
Module Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved Memories.
ICPP (1)
Lizyamma Kurian, Bermjae Choi, Paul T. Hulina, Lee D. Coraor
1994 — conf
Structured Data Access Mechanisms for a Decoupled Computer Architecture.
ICPP (2)
Ali Berrached, Paul T. Hulina, Lee D. Coraor
1992 J jnl
Design and VLSI implementation of an access processor for a decoupled architecture.
Microprocess. Microsystems
Paul T. Hulina, Lizyamma Kurian, Eugene B. John, Lee D. Coraor
1992 A* conf
Memory Latency Effects in Decoupled Architectures With a Single Data Memory Module.
ISCA
Lizyamma Kurian, Paul T. Hulina, Lee D. Coraor
1991 A* conf
Classification and Performance Evaluation of Instruction Buffering Techniques.
ISCA
Lizyamma Kurian, Paul T. Hulina, Lee D. Coraor, Dhamir N. Mannai
1991 — conf
Performance Analysis of an Address Generation Coprocessor.
ICPP (1)
Paul T. Hulina, Lee D. Coraor, Shih-Wei Sun
1990 J jnl
Coprocessor architectures for efficient address computation and memory accessing.
Comput. Syst. Sci. Eng.
Paul T. Hulina, Lee D. Coraor
1987 J jnl
A General Model for Memory-Based Finite-State Machines.
IEEE Trans. Computers
Lee D. Coraor, Paul T. Hulina, Orlando A. Morean
1987 B conf
A Hardware Memory Mapping Unit for Efficient Address Computation.
ICPP
Paul T. Hulina, Lee D. Coraor
1985 B conf
A Reconfigurable Multiprocessor.
ICPP
Lee D. Coraor, Paul T. Hulina
1973 J jnl
Synthesis of Multiple-Input Change Asynchronous Circuits Using Transition-Sensitive Flip-Flops.
IEEE Trans. Computers
Jon G. Bredeson, Paul T. Hulina
1972 J jnl
Elimination of Static and Dynamic Hazards for Multiple Input Changes in Combinatorial Switching Circuits
Inf. Control.
Jon G. Bredeson, Paul T. Hulina
1971 J jnl
Generation of Prime Implicants by Direct Multiplication.
IEEE Trans. Computers
Jon G. Bredeson, Paul T. Hulina
1971 J jnl
Generation of a Clock Pulse for Asynchronous Sequential Machines to Eliminate Critical Races.
IEEE Trans. Computers
Jon G. Bredeson, Paul T. Hulina
1970 — conf
Elimination of Static and Dynamic Hazards in Combinatorial Switching Circuits
SWAT
Jon G. Bredeson, Paul T. Hulina
1970 J jnl
On Tracey's Internal State Assignment Method.
IEEE Trans. Computers
Paul T. Hulina, Jon G. Bredeson
1970 — conf
The binary floating point digital differential analyzer.
AFIPS Fall Joint Computing Conference
James L. Elshoff, Paul T. Hulina