Paul Six

16 papers A* 4Journal 7Unranked 5
YearRankTypeTitle / Venue / Authors
1998 A* conf
Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer.
DAC
Julio Leao da Silva Jr., Chantal Ykman-Couvreur, Miguel Miranda, Kris Croes, Sven Wuytack, Gjalt G. de Jong, Francky Catthoor, Diederik Verkest, Paul Six, Hugo De Man
1998 J jnl
Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation.
J. Electron. Test.
Zohair Sahraoui, Francky Catthoor, Paul Six, Hugo De Man
1995 — conf
Search space reduction through clustering in test generation.
EURO-DAC
Zohair Sahraoui, Paul Six, Ivo Bolsens, Hugo De Man
1995 — conf
Timing optimization by bit-level arithmetic transformations.
EURO-DAC
Luc Rijnders, Zohair Sahraoui, Paul Six, Hugo De Man
1993 J jnl
Estimation of typical power of synchronous CMOS circuits using a hierarchy of simulators.
IEEE J. Solid State Circuits
Paul Vanoostende, Paul Six, Joos Vandewalle, Hugo J. De Man
1992 — conf
Flag/Condition Handling and Branch Assignment for Large Microcoded Controllers.
Synthesis for Control Dominated Circuits
Augusli Kifli, R. De Wulf, J. Zegers, Gert Goossens, Paul Six, Hugo De Man
1992 — conf
Regular Module Generation or Standard Cells: Two Alternative Implementations of a Library of Functional Building Blocks.
Synthesis for Control Dominated Circuits
Evagelos Katsadas, Zohair Sahraoui, Maryse Wouters, Veerle Derudder, Ivo Bolsens, Paul Six, Hugo De Man
1991 J jnl
DARSI: RC data reduction [VLSI simulation].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Paul Vanoostende, Paul Six, Hugo De Man
1990 A* conf
A Data Path Layout Assembler for High Performance DSP Circuits.
DAC
H. Cai, Stefaan Note, Paul Six, Hugo De Man
1990 — conf
CGE: automatic generation of controllers in the CATHEDRAL-II silicon compiler.
EURO-DAC
J. Zegers, Paul Six, Jan M. Rabaey, Hugo De Man
1989 A* conf
REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures.
DAC
I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man
1989 J jnl
REDUSA: module generation by automatic elimination of superfluous blocks in regular structures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man
1988 J jnl
CAMELEON: a process-tolerant symbolic layout system.
IEEE J. Solid State Circuits
Kris Croes, Hugo J. De Man, Paul Six
1988 J jnl
Design of a process-tolerant cell library for regular structures using symbolic layout and hierarchical compaction.
IEEE J. Solid State Circuits
Luc Rijnders, Paul Six, Hugo J. De Man
1986 A* conf
An intelligent module generator environment.
DAC
Paul Six, Luc J. M. Claesen, Jan M. Rabaey, Hugo De Man
1986 J jnl
Cathedral-II: A Silicon Compiler for Digital Signal Processing.
IEEE Des. Test
Hugo De Man, Jan M. Rabaey, Paul Six, Luc J. M. Claesen