Paul Racunas - RankMe

12 papers A* 5A 4Journal 3

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Characterizing and Mitigating Soft Errors in GPU DRAM. IEEE Micro Michael B. Sullivan, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, Stephen W. Keckler
2021	A*	`conf`	Characterizing and Mitigating Soft Errors in GPU DRAM. MICRO Michael B. Sullivan, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, Stephen W. Keckler
2020	J	`jnl`	Estimating Silent Data Corruption Rates Using a Two-Level Model. CoRR Siva Kumar Sastry Hari, Paolo Rech, Timothy Tsai, Mark Stephenson, Arslan Zulfiqar, Michael B. Sullivan, Philip P. Shirvani, Paul Racunas, Joel S. Emer, Stephen W. Keckler
2020	A	`conf`	On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors. ITC Richard Bramley, Yanxiang Huang, Guangshan Duan, Nirmal R. Saxena, Paul Racunas
2019	A	`conf`	Resiliency of automotive object detection networks on GPU architectures. ITC Atieh Lotfi, Saurabh Hukerikar, Keshav Balasubramanian, Paul Racunas, Nirmal R. Saxena, Richard Bramley, Yanxiang Huang
2018	A	`conf`	Low Overhead Tag Error Mitigation for GPU Architectures. DSN Atieh Lotfi, Nirmal R. Saxena, Richard Bramley, Paul Racunas, Philip P. Shirvani
2015	A*	`conf`	A fast and accurate analytical technique to compute the AVF of sequential bits in a processor. MICRO Steven Raasch, Arijit Biswas, Jon Stephan, Paul Racunas, Joel S. Emer
2008	J	`jnl`	Computing Accurate AVFs using ACE Analysis on Performance Models: A Rebuttal. IEEE Comput. Archit. Lett. Arijit Biswas, Paul Racunas, Joel S. Emer, Shubhendu S. Mukherjee
2007	A*	`conf`	Perturbation-based Fault Screening. HPCA Paul Racunas, Kypros Constantinides, Srilatha Manne, Shubhendu S. Mukherjee
2005	A*	`conf`	Computing Architectural Vulnerability Factors for Address-Based Structures. ISCA Arijit Biswas, Paul Racunas, Razvan Cheveresan, Joel S. Emer, Shubhendu S. Mukherjee, Ram Rangan
2003	A	`conf`	Partitioned first-level cache design for clustered microarchitectures. ICS Paul Racunas, Yale N. Patt
1997	A*	`conf`	Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order. MICRO Jared Stark, Paul Racunas, Yale N. Patt