Paul J. Hurst

78 papers C 7Misc 3Journal 59Unranked 9
YearRankTypeTitle / Venue / Authors
2022 J jnl
A Time-Interleaved SAR ADC With Signal-Independent Background Timing Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Christopher K. Su, Paul J. Hurst, Stephen H. Lewis
2020 J jnl
A Two-Step ADC With Statistical Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yi-Long Yu, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
2019 J jnl
Digital Background Calibration of a Split Current-Steering DAC.
IEEE Trans. Circuits Syst. I Regul. Pap.
David J. Stoops, Jenny Kuo, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
2018 C conf
Design of a Wideband Bandpass Stacked HBT Distributed Amplifier in InP.
ISCAS
Natalie S. Killeen, Duy P. Nguyen, Alexander N. Stameroff, Anh-Vu Pham, Paul J. Hurst
2016 C conf
An algorithmic ADC with greater than rail-to-rail input range and near-Vt supply.
ISCAS
Mo M. Zhang, Paul J. Hurst, Stephen H. Lewis
2016 J jnl
Iterative Gain Enhancement in an Algorithmic ADC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Timothy A. Monk, Paul J. Hurst, Stephen H. Lewis
2015 J jnl
An Integrator-Based Pipelined ADC With Digital Calibration.
IEEE Trans. Circuits Syst. II Express Briefs
Dong Wang, John P. Keane, Paul J. Hurst, Stephen H. Lewis
2014 J jnl
Background Adaptive Cancellation of Digital Switching Noise in a Pipelined Analog-to-Digital Converter Without Noise Sensors.
IEEE J. Solid State Circuits
Nick C.-J. Chang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
2013 J jnl
Immediate Calibration of Operational Amplifier Gain Error in Pipelined ADCs Using Extended Correlated Double Sampling.
IEEE J. Solid State Circuits
Omar A. Hafiz, Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis
2012 J jnl
A Pipelined ADC With Metastability Error Rate <10
IEEE J. Solid State Circuits
Shankar Guhados, Paul J. Hurst, Stephen H. Lewis
2012 — conf
Background adaptive cancellation of digital switching noise in pipelined ADCs without noise sensors.
CICC
Nick C.-J. Chang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
2012 J jnl
Canceling the ISI Due to Finite S/H Bandwidth in a Circular Buffer Forward Equalizer.
IEEE Trans. Circuits Syst. II Express Briefs
Nattapol Sitthimahachaikul, Lakshmi P. Rao, Paul J. Hurst
2012 J jnl
Correcting the Effects of Mismatches in Time-Interleaved Analog Adaptive FIR Equalizers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Lakshmi P. Rao, Nattapol Sitthimahachaikul, Paul J. Hurst
2012 J jnl
Overcoming the Effect of the Summation-Node Parasitic Pole in an Analog Equalizer.
IEEE Trans. Circuits Syst. I Regul. Pap.
Nattapol Sitthimahachaikul, Lakshmi P. Rao, Paul J. Hurst
2011 J jnl
A Digitally Corrected 5-mW 2-MS/s SC Delta Sigma ADC in 0.25- μ m CMOS With 94-dB SFDR.
IEEE J. Solid State Circuits
Kerry A. O'Donoghue, Paul J. Hurst, Stephen H. Lewis
2010 J jnl
A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors.
IEEE J. Solid State Circuits
Chi Ho Law, Paul J. Hurst, Stephen H. Lewis
2010 — conf
A digitally calibrated 5-mW 2-MS/s 4th-order ΔΣ ADC in 0.25-μm CMOS with 94 dB SFDR.
ESSCIRC
Kerry A. O'Donoghue, Paul J. Hurst, Stephen H. Lewis
2010 C conf
A parametric polyphase domain approach to blind calibration of timing mismatches for M-channel time-interleaved ADCs.
ISCAS
Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst
2010 C conf
Calibration of pipelined ADC gain and memory errors in an adaptively equalized receiver.
ISCAS
Mo M. Zhang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
2010 — conf
Highly programmable switched-capacitor filters using biquads with nonuniform internal clocks.
SoCC
Oliver E. Gysel, Paul J. Hurst, Stephen H. Lewis
2009 J jnl
A Full-Wave Rectifier With Integrated Peak Selection for Multiple Electrode Piezoelectric Energy Harvesters.
IEEE J. Solid State Circuits
Nathaniel J. Guilar, Rajeevan Amirtharajah, Paul J. Hurst
2009 J jnl
A Level-Crossing Analog-to-Digital Converter With Triangular Dither.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tunde Wang, Dong Wang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
2009 J jnl
Adaptive Semiblind Calibration of Bandwidth Mismatch for Two-Channel Time-Interleaved ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst
2009 — conf
An energy-aware multiple-input power supply with charge recovery for energy harvesting applications.
ISSCC
Nathaniel J. Guilar, Rajeevan Amirtharajah, Paul J. Hurst, Stephen H. Lewis
2009 J jnl
Correction of Mismatches in a Time-Interleaved Analog-to-Digital Converter in an Adaptively Equalized Digital Communication Receiver.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tsung-Heng Tsai, Paul J. Hurst, Stephen H. Lewis
2009 J jnl
Digital Calibration of a Nonlinear S/H.
IEEE J. Sel. Top. Signal Process.
Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst
2009 J jnl
Gain-Error Calibration of a Pipelined ADC in an Adaptively Equalized Baseband Receiver.
IEEE Trans. Circuits Syst. II Express Briefs
Mo M. Zhang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
2009 J jnl
Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA.
IEEE J. Solid State Circuits
Haoyue Wang, Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis
2008 — conf
A Full-Wave Rectifier for Interfacing with Multi-Phase Piezoelectric Energy Harvesters.
ISSCC
Nathaniel J. Guilar, Rajeevan Amirtharajah, Paul J. Hurst
2008 J jnl
A Programmable Impedance Matching Circuit for Voiceband Modems.
IEEE J. Solid State Circuits
Russell A. Hershbarger, Wenyan Jia, Kiam M. Tey, Kiyoshi Fukahori, Paul J. Hurst, Manprit Kapoor
2008 J jnl
DAC Quantization-Noise Cancellation in an Echo-Canceling Transceiver.
IEEE Trans. Circuits Syst. II Express Briefs
Paul J. Hurst, Andy Norrell
2007 J jnl
A Passive Switched-Capacitor Finite-Impulse-Response Equalizer.
IEEE J. Solid State Circuits
Nathaniel J. Guilar, Frank Lau, Paul J. Hurst, Stephen H. Lewis
2007 C conf
Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved A/D Converter.
ISCAS
Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst
2006 J jnl
Bandwidth Mismatch and Its Correction in Time-Interleaved Analog-to-Digital Converters.
IEEE Trans. Circuits Syst. II Express Briefs
Tsung-Heng Tsai, Paul J. Hurst, Stephen H. Lewis
2006 J jnl
Digital background calibration for memory effects in pipelined analog-to-digital converters.
IEEE Trans. Circuits Syst. I Regul. Pap.
John P. Keane, Paul J. Hurst, Stephen H. Lewis
2006 C conf
Effect of nonlinearity in the CMFB circuit that uses the differential-difference amplifier.
ISCAS
Mo M. Zhang, Paul J. Hurst
2005 J jnl
A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration.
IEEE J. Solid State Circuits
Carl R. Grace, Paul J. Hurst, Stephen H. Lewis
2005 — conf
A 200 MS/s passive switched-capacitor FIR equalizer using a time-interleaved topology.
CICC
Nathaniel J. Guilar, Pak-Kim Lau, Paul J. Hurst, Stephen H. Lewis
2005 J jnl
Background interstage gain calibration technique for pipelined ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap.
John P. Keane, Paul J. Hurst, Stephen H. Lewis
2005 — conf
Convergence analysis of a background interstage gain calibration technique for pipelined ADCs.
ISCAS (4)
Dong Wang, John P. Keane, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
2005 J jnl
Correction to "Calibration of Sample-Time Error in a Two-Channel Time-Interleaved Analog-to-Digital Converter".
IEEE Trans. Circuits Syst. I Regul. Pap.
Shafiq M. Jamal, Daihong Fu, Mahendra P. Singh, Paul J. Hurst, Stephen H. Lewis
2004 J jnl
A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration.
IEEE J. Solid State Circuits
Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis
2004 J jnl
A mixed-signal approach for tuning continuous-time low-pass filters.
IEEE Trans. Circuits Syst. II Express Briefs
Anthony Tong, Paul J. Hurst
2004 J jnl
Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shafiq M. Jamal, Daihong Fu, Mahendra P. Singh, Paul J. Hurst, Stephen H. Lewis
2004 J jnl
Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Paul J. Hurst, Stephen H. Lewis, John P. Keane, Farbod Aram, Kenneth C. Dyer
2004 J jnl
Reconstruction of band-limited periodic nonuniformly sampled signals through multirate filter banks.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ryan Strong Prendergast, Bernard C. Levy, Paul J. Hurst
2003 — conf
A 12-bit 20-MS/s pipelined ADC with nested digital background calibration.
CICC
Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis
2003 J jnl
Analog timing recovery for a noise-predictive decision-feedback equalizer.
IEEE J. Solid State Circuits
John P. Keane, Michael Q. Le, Paul J. Hurst
2003 J jnl
Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue.
IEEE J. Solid State Circuits
Eric B. Blecker, Thomas M. McDonald, Ozan E. Erdogan, Paul J. Hurst, Stephen H. Lewis
2002 J jnl
A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration.
IEEE J. Solid State Circuits
Shafiq M. Jamal, Daihong Fu, Nick C.-J. Chang, Paul J. Hurst, Stephen H. Lewis
2002 J jnl
An adaptive analog noise-predictive decision-feedback equalizer.
IEEE J. Solid State Circuits
Michael Q. Le, Paul J. Hurst, John P. Keane
2001 — conf
A mixed-signal tuning approach for continuous-time LPFs.
ISCAS (1)
Anthony Tong, Paul J. Hurst
2000 J jnl
A CMOS HDSL2 analog front-end.
IEEE J. Solid State Circuits
Amit Gattani, David W. Cline, Paul J. Hurst, Paul M. Mosinskis
2000 J jnl
A CMOS analog timing recovery circuit for PRML detectors.
IEEE J. Solid State Circuits
Pierte Roo, Richard R. Spencer, Paul J. Hurst
1999 J jnl
A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD.
IEEE J. Solid State Circuits
Ozan E. Erdogan, Paul J. Hurst, Stephen H. Lewis
1999 J jnl
An analog DFE for disk drives using a mixed-signal integrator.
IEEE J. Solid State Circuits
Michael Q. Le, Paul J. Hurst, Kenneth C. Dyer
1998 J jnl
A digital background calibration technique for time-interleaved analog-to-digital converters.
IEEE J. Solid State Circuits
Daihong Fu, Kenneth C. Dyer, Stephen H. Lewis, Paul J. Hurst
1998 J jnl
An analog background calibration technique for time-interleaved analog-to-digital converters.
IEEE J. Solid State Circuits
Kenneth C. Dyer, Daihong Fu, Stephen H. Lewis, Paul J. Hurst
1997 J jnl
A fully differential comparator using a switched-capacitor differencing circuit with common-mode rejection.
IEEE J. Solid State Circuits
Tanchu Shih, Lawrence Der, Stephen H. Lewis, Paul J. Hurst
1997 J jnl
A mixed-signal RAM decision-feedback equalizer for disk drives.
IEEE J. Solid State Circuits
Bret C. Rothenberg, James E. C. Brown, Paul J. Hurst, Stephen H. Lewis
1997 J jnl
A mixed-signal decision-feedback equalizer that uses a look-ahead architecture.
IEEE J. Solid State Circuits
Ravinder S. Kajley, Paul J. Hurst, James E. C. Brown
1997 J jnl
A second-order double-sampled delta-sigma modulator using individual-level averaging.
IEEE J. Solid State Circuits
Chuc K. Thanh, Stephen H. Lewis, Paul J. Hurst
1996 J jnl
A 35 Mb/s mixed-signal decision-feedback equalizer for disk drives in 2-μm CMOS.
IEEE J. Solid State Circuits
James E. C. Brown, Paul J. Hurst, Lawrence Der
1996 J jnl
A second-order double-sampled delta-sigma modulator using additive-error switching.
IEEE J. Solid State Circuits
Ted Vinko Burmas, Kenneth C. Dyer, Paul J. Hurst, Stephen H. Lewis
1995 J jnl
A 20-Msample/s switched-capacitor finite-impulse-response filter using a transposed structure.
IEEE J. Solid State Circuits
Bret C. Rothenberg, Stephen H. Lewis, Paul J. Hurst
1995 J jnl
A programmable clock generator that uses noise shaping and its application in switched-capacitor filters.
IEEE J. Solid State Circuits
Paul J. Hurst, Bret C. Rothenberg
1995 J jnl
An 80-Msample/s video switched-capacitor filter using a parallel biquadratic structure.
IEEE J. Solid State Circuits
Steven K. Berg, Paul J. Hurst, Stephen H. Lewis
1994 C conf
A Comparison of Analog DFE Architectures for Disk-Drive Applications.
ISCAS
James E. C. Brown, Paul J. Hurst, Lawrence Der, Iskender Agi
1993 J jnl
A switched-capacitor delta-sigma modulator with reduced sensitivity to op-amp gain.
IEEE J. Solid State Circuits
Paul J. Hurst, Roger A. Levinson, David J. Block
1993 J jnl
An image processing IC for backprojection and spatial histogramming in a pipelined array.
IEEE J. Solid State Circuits
Iikender Agi, Paul J. Hurst, K. Wayne Current
1992 J jnl
A VLSI processor for parallel contour tracing.
IEEE Trans. Signal Process.
Iskender Agi, Paul J. Hurst, Anil K. Jain
1992 J jnl
High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architecture.
IEEE Trans. Circuits Syst. Video Technol.
Eric Shieh, K. Wayne Current, Paul J. Hurst, Iskender Agi
1990 Misc conf
A VLSI architecture for two-dimensional Radon transform computations.
ICASSP
Paul J. Hurst, K. Wayne Current, Iskender Agi, Eric Shieh
1990 J jnl
A single-chip 5-V 2400-b/s modem.
IEEE J. Solid State Circuits
Stephen D. Levy, Paul J. Hurst, Peicheng Ju, John M. Huggins, Christopher R. Cole
1990 J jnl
An evaluation of Radon transform computations using DSP chips.
Mach. Vis. Appl.
K. Wayne Current, Paul J. Hurst, Eric Shieh, Iskender Agi
1989 Misc conf
A Radon transform computer for multidimensional signal processing.
ICASSP
Stephen G. Azevedo, James M. Brase, Harry E. Martz, Anil K. Jain, K. Wayne Current, Paul J. Hurst
1988 J jnl
An analog front end for v.22bis modems.
IEEE J. Solid State Circuits
Paul J. Hurst, Thomas J. Glad, J. Jeff Illgner, George F. Landsburg
1988 Misc conf
An expandable VLSI processor array approach to contour tracing.
ICASSP
Iskender Agi, Paul J. Hurst, Anil K. Jain