Paul Chow - RankMe

167 papers A* 8A 28B 21C 3Misc 25Journal 39Unranked 42

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Derek Chiou. IEEE Micro Doug Burger, Paul Chow, Joel S. Emer, Mark D. Hill, James C. Hoe, Masato Motomura
2024	J	`jnl`	DDC: A Vision for a Disaggregated Datacenter. CoRR Mohammad Ewais, Paul Chow
2024	J	`jnl`	The Feasibility of Implementing Large-Scale Transformers on Multi-FPGA Platforms. CoRR Yu Gao, Juan Camilo Vega, Paul Chow
2024	J	`jnl`	The Software-Centric Approach of SYNERGY: Technical Perspective. Commun. ACM Paul Chow
2023	C	`conf`	A Lightweight Routing Layer Using a Reliable Link-Layer Protocol. CloudCom Qiangfeng Shen, Paul Chow
2023	J	`jnl`	A Lightweight Routing Layer Using a Reliable Link-Layer Protocol. CoRR Qianfeng Shen, Paul Chow
2023	J	`jnl`	Disaggregated Memory in the Datacenter: A Survey. IEEE Access Mohammad Ewais, Paul Chow
2023	B	`conf`	Partitioning Large-Scale, Multi-FPGA Applications for the Data Center. FPL Mohammadmahdi Mazraeli, Yu Gao, Paul Chow
2023	J	`jnl`	RIFL: A Reliable Link Layer Network Protocol for Data Center Communication. CoRR Qianfeng Shen, Jun Zheng, Paul Chow
2022	—	`conf`	Parallel CRC On An FPGA At Terabit Speeds. FPT Qianfeng Clark Shen, Juan Camilo Vega, Paul Chow
2022	J	`jnl`	RIFL: a reliable link layer network protocol for data center communication. JOCN Qianfeng Shen, Jun Zheng, Paul Chow
2022	J	`jnl`	The Future of FPGA Acceleration in Datacenters and the Cloud. ACM Trans. Reconfigurable Technol. Syst. Christophe Bobda, Joel Mandebi Mbongue, Paul Chow, Mohammad Ewais, Naif Tarafdar, Juan Camilo Vega, Ken Eguro, Dirk Koch, Suranga Handagala, Miriam Leeser, Martin C. Herbordt, Hafsah Shahzad, H. Peter Hofstee, Burkhard Ringlein, Jakub Szefer, Ahmed Sanaullah, Russell Tessier
2021	—	`conf`	A Framework Integrating FPGAs in VNF Networks. NoF Mohammad Ewais, Juan Camilo Vega, Alberto Leon-Garcia, Paul Chow
2021	J	`jnl`	A PGAS Communication Library for Heterogeneous Clusters. CoRR Varun Sharma, Paul Chow
2021	A	`conf`	Exploring PGAS Communication for Heterogeneous Clusters with FPGAs. FPGA Varun Sharma, Paul Chow
2021	Misc	`conf`	FFIVE: An FPGA Framework for Interactive VNF Environments. FCCM Juan Camilo Vega, Mohammad Ewais, Alberto Leon-Garcia, Paul Chow
2021	J	`jnl`	FPGA Implementation of an Improved OMP for Compressive Sensing Reconstruction. IEEE Trans. Very Large Scale Integr. Syst. Jun Li, Paul Chow, Yuanxi Peng, Tian Jiang
2021	—	`ed.`	HEART '21: 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Virtual Event, Germany, 21-23 June, 2021. HEART Christian Plessl, Paul Chow, Marco Platzner
2021	A	`conf`	Interactive Debugging at IP Block Interfaces in FPGAs. FPGA Marco Antonio Merlini, Isamu Poy, Paul Chow
2021	B	`conf`	Pharos: a Multi-FPGA Performance Monitor. FPL Arzhang Rafii, Welson Sun, Paul Chow
2021	Misc	`conf`	Pharos: a Performance Monitor for Multi-FPGA Systems. FCCM Arzhang Rafii, Paul Chow, Welson Sun
2021	A	`conf`	RIFL: A Reliable Link Layer Network Protocol for FPGA-to-FPGA Communication. FPGA Qianfeng Clark Shen, Jun Zheng, Paul Chow
2020	Misc	`conf`	AIgean: An Open Framework for Machine Learning on Heterogeneous Clusters. FCCM Naif Tarafdar, Giuseppe Di Guglielmo, Philip C. Harris, Jeffrey D. Krupa, Vladimir Loncar, Dylan S. Rankin, Nhan Tran, Zhenbin Wu, Qianfeng Shen, Paul Chow
2020	Misc	`conf`	FFShark: A 100G FPGA Implementation of BPF Filtering for Wireshark. FCCM Juan Camilo Vega, Marco Antonio Merlini, Paul Chow
2020	Misc	`conf`	Hierarchical Modelling of Generators in Design-Space Exploration. FCCM Charles Lo, Paul Chow
2020	Misc	`conf`	SHIP: Storage for Hybrid Interconnected Processors. FCCM Juan Camilo Vega, Qianfeng Clark Shen, Paul Chow
2019	A	`conf`	A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the Data Center. FPGA Nariman Eskandari, Naif Tarafdar, Daniel Ly-Ma, Paul Chow
2019	J	`jnl`	Accelerating Apache Spark with FPGAs. Concurr. Comput. Pract. Exp. Ehsan Ghasemi, Paul Chow
2019	B	`conf`	Introducing ReCPRI: A Field Re-configurable Protocol for Backhaul Communication in a Radio Access Network. IM Juan Camilo Vega, Qianfeng Shen, Alberto Leon-Garcia, Paul Chow
2019	Misc	`conf`	Sonar: Writing Testbenches through Python. FCCM Varun Sharma, Naif Tarafdar, Paul Chow
2019	A	`conf`	The Network Management Unit (NMU): Securing Network Access for Direct-Connected FPGAs. FPGA Daniel Rozhko, Paul Chow
2018	Misc	`conf`	A High-Level Synthesis Case Study on Light Propagation Simulation in Turbid Media. FCCM Abdul-Amir Yassine, Yasmin Afsharnejad, Omar Ragheb, Vaughn Betz, Paul Chow
2018	J	`jnl`	Designing for FPGAs in the Cloud. IEEE Des. Test Naif Tarafdar, Nariman Eskandari, Thomas Lin, Paul Chow
2018	J	`jnl`	Galapagos: A Full Stack Approach to FPGA Integration in the Cloud. IEEE Micro Naif Tarafdar, Nariman Eskandari, Varun Sharma, Charles Lo, Paul Chow
2018	—	`conf`	HLS-based FPGA Acceleration of Light Propagation Simulation in Turbid Media. HEART Yasmin Afsharnejad, Abdul-Amir Yassine, Omar Ragheb, Paul Chow, Vaughn Betz
2018	B	`conf`	Multi-fidelity Optimization for High-Level Synthesis Directives. FPL Charles Lo, Paul Chow
2017	—	`conf`	An FPGA-based processor for training convolutional neural networks. FPT Zhiqiang Liu, Yong Dou, Jingfei Jiang, Qiang Wang, Paul Chow
2017	—	`conf`	Build fast, trade fast: FPGA-based high-frequency trading using high-level synthesis. ReConFig Andrew Boutros, Brett Grady, Mustafa Abbas, Paul Chow
2017	—	`conf`	Building the Reconfigurable Cloud Ecosystem. ETCD@ASPLOS Paul Chow
2017	—	`conf`	Enabling FPGAs as a True Device in the OpenCL Standard: Bridging the Gap for FPGAs. IWOCL Vincent Mirian, Paul Chow
2017	A	`conf`	Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center. FPGA Naif Tarafdar, Thomas Lin, Eric Fukuda, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow
2017	C	`conf`	Enabling network function virtualization over heterogeneous resources. APNOMS Thomas Lin, Naif Tarafdar, Byungchul Park, Paul Chow, Alberto Leon-Garcia
2017	—	`conf`	FPGA-based training of convolutional neural networks with a reduced precision floating-point library. FPT Roberto DiCecco, Lin Sun, Paul Chow
2017	B	`conf`	Heterogeneous virtualized network function framework for the data center. FPL Naif Tarafdar, Thomas Lin, Nariman Eskandari, David Lion, Alberto Leon-Garcia, Paul Chow
2017	A	`conf`	Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules. FPGA Daniel Rozhko, Geoffrey Elliott, Daniel Ly-Ma, Paul Chow, Hans-Arno Jacobsen
2017	—	`conf`	Task replication and control for highly parallel in-memory stores. MEMSYS Fernando Martin del Campo, Paul Chow
2016	A	`conf`	A Scalable Heterogeneous Dataflow Architecture For Big Data Analytics Using FPGAs (Abstract Only). FPGA Ehsan Ghasemi, Paul Chow
2016	Misc	`conf`	Accelerating Apache Spark Big Data Analysis with FPGAs. FCCM Ehsan Ghasemi, Paul Chow
2016	—	`conf`	Accelerating Apache Spark Big Data Analysis with FPGAs. UIC/ATC/ScalCom/CBDCom/IoP/SmartWorld Ehsan Ghasemi, Paul Chow
2016	J	`jnl`	CORDIC-Based Enhanced Systolic Array Architecture for QR Decomposition. ACM Trans. Reconfigurable Technol. Syst. Jianfeng Zhang, Paul Chow, Hengzhu Liu
2016	J	`jnl`	Caffeinated FPGAs: FPGA Framework For Convolutional Neural Networks. CoRR Roberto DiCecco, Griffin Lacey, Jasmina Vasiljevic, Paul Chow, Graham W. Taylor, Shawki Areibi
2016	—	`conf`	Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks. FPT Roberto DiCecco, Griffin Lacey, Jasmina Vasiljevic, Paul Chow, Graham W. Taylor, Shawki Areibi
2016	—	`conf`	Extracting Designs of Secure IPs Using FPGA CAD Tools. ACM Great Lakes Symposium on VLSI Vincent Mirian, Paul Chow
2016	B	`conf`	Model-based optimization of High Level Synthesis directives. FPL Charles Lo, Paul Chow
2015	J	`jnl`	An Enhanced Adaptive Recoding Rotation CORDIC. ACM Trans. Reconfigurable Technol. Syst. Jianfeng Zhang, Paul Chow, Hengzhu Liu
2015	—	`conf`	Architecture Exploration for Data Intensive Applications. MEMSYS Fernando Martin del Campo, Paul Chow
2015	—	`conf`	Evaluating shared virtual memory in an OpenCL framework for embedded systems on FPGAs. ReConFig Vincent Mirian, Paul Chow
2015	A	`conf`	Expanding OpenFlow Capabilities with Virtualized Reconfigurable Hardware. FPGA Stuart Byma, Naif Tarafdar, Talia Xu, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow
2015	—	`conf`	Exploring pipe implementations using an OpenCL framework for FPGAs. FPT Vincent Mirian, Paul Chow
2015	—	`conf`	FPGA implementation of low-power and high-PSNR DCT/IDCT architecture based on adaptive recoding CORDIC. FPT Jianfeng Zhang, Paul Chow, Hengzhu Liu
2015	—	`conf`	OpenCL library of stream memory components targeting FPGAs. FPT Jasmina Vasiljevic, Ralph Wittig, Paul Schumacher, Jeff Fifield, Fernando Martinez-Vallina, Henry Styles, Paul Chow
2015	—	`conf`	UT-OCL: an OpenCL framework for embedded systems using xilinx FPGAs. ReConFig Vincent Mirian, Paul Chow
2014	—	`conf`	A Heterogeneous GASNet Implementation for FPGA-accelerated Computing. PGAS Ruediger Willenberg, Paul Chow
2014	J	`jnl`	A Software Parallel Programming Approach to FPGA-Accelerated Computing. CoRR Ruediger Willenberg, Paul Chow
2014	—	`conf`	An efficient FPGA implementation of QR decomposition using a novel systolic array architecture based on enhanced vectoring CORDIC. FPT Jianfeng Zhang, Paul Chow, Hengzhu Liu
2014	J	`jnl`	Benefits of Adding Hardware Support for Broadcast and Reduce Operations in MPSoC Applications. ACM Trans. Reconfigurable Technol. Syst. Yuanxi Peng, Manuel Saldaña, Christopher A. Madill, Xiaofeng Zou, Paul Chow
2014	Misc	`conf`	FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack. FCCM Stuart Byma, J. Gregory Steffan, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow
2014	A	`conf`	MPack: global memory optimization for stream applications in high-level synthesis. FPGA Jasmina Vasiljevic, Paul Chow
2014	J	`jnl`	Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method. IEEE Trans. Very Large Scale Integr. Syst. Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang, Shaojun Wei
2014	B	`conf`	Using an OpenCL framework to evaluate interconnect implementations on FPGAs. FPL Vincent Mirian, Paul Chow
2014	B	`conf`	Using buffer-to-BRAM mapping approaches to trade-off throughput vs. memory use. FPL Jasmina Vasiljevic, Paul Chow
2014	Misc	`conf`	Virtualized Reconfigurable Hardware Resources in the SAVI Testbed. TRIDENTCOM Stuart Byma, Hadi Bannazadeh, Alberto Leon-Garcia, J. Gregory Steffan, Paul Chow
2013	A	`conf`	A remote memory access infrastructure for global address space programming models in FPGAs. FPGA Ruediger Willenberg, Paul Chow
2013	B	`conf`	NetThreads-10G: Software packet processing on NetFPGA-10G in a virtualized networking environment demonstration abstract. FPL Stuart Byma, J. Gregory Steffan, Paul Chow
2013	B	`conf`	SimXMD: Simulation-based HW/SW co-debugging. FPL Ruediger Willenberg, Paul Chow
2013	B	`conf`	Simulation-based HW/SW co-debugging for field-programmable systems-on-chip. FPL Ruediger Willenberg, Paul Chow
2013	—	`conf`	Why Put FPGAs in your CPU socket? FPT Paul Chow
2013	—	`conf`	ZCluster: A Zynq-based Hadoop cluster. FPT Zhongduo Lin, Paul Chow
2012	—	`conf`	A high-performance architecture for training Viola-Jones object detectors. FPT Charles Lo, Paul Chow
2012	—	`conf`	An implementation of a directory protocol for a cache coherent system on FPGAs. ReConFig Vincent Mirian, Paul Chow
2012	A	`conf`	FCache: a system for cache coherent processing on FPGAs. FPGA Vincent Mirian, Paul Chow
2012	B	`conf`	K-means implementation on FPGA for high-dimensional data using triangle inequality. FPL Zhongduo Lin, Charles Lo, Paul Chow
2012	—	`conf`	Managing mutex variables in a cache-coherent shared-memory system for FPGAs. FPT Vincent Mirian, Paul Chow
2012	A	`conf`	OpenCL memory infrastructure for FPGAs (abstract only). FPGA S. Alexander Chin, Paul Chow
2012	—	`conf`	SimXMD: Integrated debugging of C code and hardware components. FPT Ruediger Willenberg, Paul Chow
2012	—	`conf`	Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Python method. FPT Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang, Shaojun Wei
2012	J	`jnl`	Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms. Int. J. Reconfigurable Comput. Manuel Saldaña, Arun Patel, Hao Jun Liu, Paul Chow
2011	A	`conf`	Building a multi-FPGA virtualized restricted boltzmann machine architecture using embedded MPI. FPGA Charles Lo, Paul Chow
2011	J	`jnl`	FPGA Acceleration of MultiFactor CDO Pricing. ACM Trans. Reconfigurable Technol. Syst. Alexander Kaganov, Asif Lakhany, Paul Chow
2011	B	`conf`	Hardware Support for Broadcast and Reduce in MPSoC. FPL Yuanxi Peng, Manuel Saldaña, Paul Chow
2011	Misc	`ed.`	IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2011, Salt Lake City, Utah, USA, 1-3 May 2011 FCCM Paul Chow, Michael J. Wirthlin
2011	J	`jnl`	Leveraging reconfigurability in the hardware/software codesign process. ACM Trans. Reconfigurable Technol. Syst. Lesley Shannon, Paul Chow
2011	B	`conf`	Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method. FPL Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang
2010	A	`conf`	Acceleration of an analytical approach to collateralized debt obligation pricing. FPGA Dharmendra P. Gupta, Paul Chow
2010	J	`jnl`	High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann Machines. IEEE Trans. Neural Networks Daniel Le Ly, Paul Chow
2010	Misc	`conf`	Integrating High-Level Synthesis into MPI. FCCM Andrew W. H. House, Manuel Saldaña, Paul Chow
2010	J	`jnl`	MPI as a Programming Model for High-Performance Reconfigurable Computers. ACM Trans. Reconfigurable Technol. Syst. Manuel Saldaña, Arun Patel, Christopher A. Madill, Daniel Nunes, Danyao Wang, Paul Chow, Ralph Wittig, Henry Styles, Andrew Putnam
2010	—	`conf`	Using Partial Reconfiguration in an Embedded Message-Passing System. ReConFig Manuel Saldaña, Arun Patel, Hao Jun Liu, Paul Chow
2010	Misc	`conf`	Virtualized Application Networking Infrastructure. TRIDENTCOM Hadi Bannazadeh, Alberto Leon-Garcia, Keith Redmond, Gordon Tam, Arbab Khan, Mingliang Ma, Saleh Dani, Paul Chow
2009	J	`jnl`	A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems. Int. J. Reconfigurable Comput. Manuel Saldaña, Emanuel Ramalho, Paul Chow
2009	A	`conf`	A high-performance FPGA architecture for restricted boltzmann machines. FPGA Daniel Le Ly, Paul Chow
2009	B	`conf`	A multi-FPGA architecture for stochastic Restricted Boltzmann Machines. FPL Daniel Le Ly, Paul Chow
2009	Misc	`conf`	FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy. FCCM Jason Luu, Keith Redmond, William Lo, Paul Chow, Lothar Lilge, Jonathan Rose
2009	—	`conf`	Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture. ReConFig Jiang Jiang, Vincent Mirian, Kam Pui Tang, Paul Chow, Zuocheng Xing
2009	A	`ed.`	Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009 FPGA Paul Chow, Peter Y. K. Cheung
2009	—	`conf`	Programming the Nallatech Xeon + multi-FPGA heterogeneous platform. Hot Chips Symposium Paul Chow, Manuel Saldaña, Arun Patel, Christopher A. Madill
2009	—	`conf`	The challenges of using an embedded MPI for hardware-based processing nodes. FPT Daniel Le Ly, Manuel Saldaña, Paul Chow
2008	—	`conf`	A Message-Passing Hardware/Software Co-simulation Environment to Aid in Reconfigurable Computing Design Using TMD-MPI. ReConFig Manuel Saldaña, Emanuel Ramalho, Paul Chow
2008	—	`conf`	A profiler for a heterogeneous multi-core multi-FPGA system. FPT Daniel Nunes, Manuel Saldaña, Paul Chow
2008	J	`jnl`	Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy. ACM Trans. Embed. Comput. Syst. Tor M. Aamodt, Paul Chow
2008	B	`conf`	FPGA acceleration of Monte-Carlo based credit derivative pricing. FPL Alexander Kaganov, Paul Chow, Asif Lakhany
2008	Misc	`conf`	Investigation of Programming Models for Emerging FPGA-Based High Performance Computing Systems. FCCM Andrew W. H. House, Paul Chow
2008	—	`conf`	MPI as an abstraction for software-hardware interaction for HPRCs. HPRCTA@SC Manuel Saldaña, Arun Patel, Christopher A. Madill, Daniel Nunes, Danyao Wang, Henry Styles, Andrew Putnam, Ralph Wittig, Paul Chow
2008	A	`ed.`	Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008 FPGA Mike Hutton, Paul Chow
2007	—	`conf`	A CMOS Image Sensor for DNA Microarrays. CICC Samir Parikh, P. Glenn Gulak, Paul Chow
2007	—	`conf`	An FPGA Implementation of Reciprocal Sums for SPME. ERSA Sam Lee, Paul Chow
2007	—	`conf`	Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor. ACM Great Lakes Symposium on VLSI Chichyang Chen, Paul Chow
2007	A	`conf`	Integrating FPGAs in high-performance computing: introduction. FPGA Paul Chow, Mike Hutton
2007	A	`conf`	Optimization of data prefetch helper threads with path-expression based statistical modeling. ICS Tor M. Aamodt, Paul Chow
2007	J	`jnl`	Routability of Network Topologies in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Manuel Saldaña, Lesley Shannon, Jia Shuo Yue, Sikang Bian, John Craig, Paul Chow
2007	J	`jnl`	SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse. IEEE Trans. Very Large Scale Integr. Syst. Lesley Shannon, Paul Chow
2006	Misc	`conf`	A Scalable FPGA-based Multiprocessor. FCCM Arun Patel, Christopher A. Madill, Manuel Saldaña, Chris Comis, Régis Pomès, Paul Chow
2006	B	`conf`	A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification. FPL Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow
2006	—	`conf`	Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI. ReConFig Manuel Saldaña, Daniel Nunes, Emanuel Ramalho, Paul Chow
2006	B	`conf`	TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs. FPL Manuel Saldaña, Paul Chow
2006	A	`conf`	The routability of multiprocessor network topologies in FPGAs. FPGA Manuel Saldaña, Lesley Shannon, Paul Chow
2006	—	`conf`	The routability of multiprocessor network topologies in FPGAs. SLIP Manuel Saldaña, Lesley Shannon, Paul Chow
2005	—	`conf`	Designing an FPGA SoC Using a Standardized IP Block Interface. FPT Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow
2005	B	`conf`	Leveraging Reconfigurability in the Design Process. FPL Lesley Shannon, Paul Chow
2005	Misc	`conf`	Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller. FCCM Lesley Shannon, Paul Chow
2004	A	`conf`	FPGA-based supercomputing: an implementation for molecular dynamics. FPGA Ian Kuon, Navid Azizi, Ahmad Darabiha, Aaron Egier, Paul Chow
2004	A*	`conf`	Hardware Support for Prescient Instruction Prefetch. HPCA Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen
2004	—	`conf`	Maximizing system performance: using reconfigurability to monitor system communications. FPT Lesley Shannon, Paul Chow
2004	Misc	`conf`	Reconfigurable Molecular Dynamics Simulator. FCCM Navid Azizi, Ian Kuon, Aaron Egier, Ahmad Darabiha, Paul Chow
2004	A	`conf`	Using reconfigurability to achieve real-time profiling for hardware/software codesign. FPGA Lesley Shannon, Paul Chow
2003	A*	`conf`	A framework for modeling and optimization of prescient instruction prefetch. SIGMETRICS Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen
2003	Misc	`conf`	Standardizing the Performance Assessment of Reconfigurable Processor Architectures. FCCM Lesley Shannon, Paul Chow
2001	A	`conf`	The effect of reconfigurable units in superscalar processors. FPGA Jorge E. Carrillo, Paul Chow
2000	J	`jnl`	A Scheduler ASIC for a Programmable Packet Switch. IEEE Micro L. Louis Zhang, Brent Beacham, Massoud R. Hashemi, Paul Chow, Alberto Leon-Garcia
2000	Misc	`conf`	Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation. CASES Tor M. Aamodt, Paul Chow
1999	A	`conf`	DES Cracking on the Transmogrifier 2a. CHES Ivan Hamer, Paul Chow
1999	A	`conf`	Memory Interfacing and Instruction Specification for Reconfigurable Processors. FPGA Jeffrey A. Jacob, Paul Chow
1999	J	`jnl`	The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning. Int. J. Parallel Program. Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
1999	J	`jnl`	The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout. IEEE Trans. Very Large Scale Integr. Syst. Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard Páez-Monzón, Immanuel Rahardja
1999	J	`jnl`	The design of an SRAM-based field-programmable gate array. I. Architecture. IEEE Trans. Very Large Scale Integr. Syst. Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard Páez-Monzón, Immanuel Rahardja
1998	J	`jnl`	The Transmogrifier-2: a 1 million gate rapid-prototyping system. IEEE Trans. Very Large Scale Integr. Syst. David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow
1997	A*	`conf`	Memory-System Design Considerations for Dynamically-Scheduled Processors. ISCA Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
1997	A*	`conf`	The Multicluster Architecture: Reducing Cycle Time Through Partitioning. MICRO Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
1997	A	`conf`	The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System. FPGA David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow
1996	A*	`conf`	Exploiting Dual Data-Memory Banks in Digital Signal Processors. ASPLOS Mazen A. R. Saghir, Paul Chow, Corinna G. Lee
1996	Misc	`conf`	OneChip: an FPGA processor with reconfigurable logic. FCCM Ralph Wittig, Paul Chow
1996	Misc	`conf`	RACER: a reconfigurable constraint-length 14 Viterbi decoder. FCCM David Yeh, Gennady Feygin, Paul Chow
1996	A*	`conf`	Register File Design Considerations in Dynamically Scheduled Processors. HPCA Keith I. Farkas, Norman P. Jouppi, Paul Chow
1995	A	`conf`	A Field-Programmable Mixed-Analog-Digital Array. FPGA Paul Chow, P. Glenn Gulak
1995	A*	`conf`	How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors? HPCA Keith I. Farkas, Norman P. Jouppi, Paul Chow
1994	—	`conf`	Application-driven design of DSP architectures and compilers. ICASSP (2) Mazen A. R. Saghir, Paul Chow, Corinna G. Lee
1994	B	`conf`	Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression. Data Compression Conference Gennady Feygin, P. Glenn Gulak, Paul Chow
1994	J	`jnl`	Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding. Inf. Process. Manag. Gennady Feygin, P. Glenn Gulak, Paul Chow
1993	C	`conf`	A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. ISCAS Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton
1993	J	`jnl`	A multiprocessor architecture for Viterbi decoders with linear speedup. IEEE Trans. Signal Process. Gennady Feygin, Patrick Glenn Gulak, Paul Chow
1993	B	`conf`	Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding. Data Compression Conference Gennady Feygin, P. Glenn Gulak, Paul Chow
1992	J	`jnl`	The effect of logic block architecture on FPGA performance. IEEE J. Solid State Circuits Satwant Singh, Jonathan Rose, Paul Chow, David M. Lewis
1991	Misc	`conf`	A streamlined DSP microprocessor architecture. ICASSP Michael Takefman, Paul Chow
1991	Misc	`conf`	Generalized cascade Viterbi decoder-a locally connected multiprocessor with linear speed-up. ICASSP Gennady Feygin, Patrick Glenn Gulak, Paul Chow
1990	J	`jnl`	Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency. IEEE J. Solid State Circuits Jonathan Rose, Robert J. Francis, David M. Lewis, Paul Chow
1987	A*	`conf`	Architectural Tradeoffs in the Design of MIPS-X. ISCA Paul Chow, Mark Horowitz
1983	J	`jnl`	A Pipelined Distributed Arithmetic PFFT Processor. IEEE Trans. Computers Paul Chow, Zvonko G. Vranesic, Jui Lin Yen