Paul Beckett

35 papers A 2B 1C 5Misc 2Journal 9Unranked 16
YearRankTypeTitle / Venue / Authors
2023 J jnl
Wavelength-selective wavefront shaping by metasurface.
Frontiers Inf. Technol. Electron. Eng.
Zixin Cai, Xin He, Xin Liu, Shijie Tu, Xinjie Sun, Paul Beckett, Aditya Dubey, Arnan Mitchell, Guanghui Ren, Xu Liu, Xiang Hao
2022 — conf
Optimising Power-Performance in SOI-based Null Convention Logic.
ICICDT
Nguyen Le Huy, Paul Beckett
2019 Misc conf
TIARA: technology integrated apnea respiration analyser.
UbiComp
Abdur Rahim Mohammad Forkan, Flora D. Salim, Russell Conduit, Paul Beckett, Stephen R. Robinson
2018 J jnl
A Physical Unclonable Function With Redox-Based Nanoionic Resistive Memory.
IEEE Trans. Inf. Forensics Secur.
Jeeson Kim, Taimur Ahmed, Hussein Nili, Jiawei Yang, Doo Seok Jeong, Paul Beckett, Sharath Sriram, Damith Chinthana Ranasinghe, Omid Kavehei
2018 J jnl
Clock-Less DFT-Less Test Strategy for Null Convention Logic.
IEEE Trans. Emerg. Top. Comput.
Nastaran Nemati, Paul Beckett, Mark C. Reed, Karl M. Fant
2018 — conf
FPGA Based Implementation and Area Performance Analysis of Sigma-Delta Modulated Steepest Algorithm for Channel Equalization.
ICSPCS
Tayab Din Memon, Aneela Pathan, Paul Beckett
2017 — conf
The Bel array: asynchronous fine-grained reconfigurable co-processing.
ACSW
Andrew Przybylski, Kashfia Haque, Paul Beckett
2017 — conf
Usability of LoRaWAN Technology in a Central Business District.
VTC Spring
Peter J. Radcliffe, Karina Gomez Chavez, Paul Beckett, Justin Spangaro, Conrad Jakob
2016 J jnl
A Physical Unclonable Function with Redox-based Nanoionic Resistive Memory.
CoRR
Jeeson Kim, Taimur Ahmed, Hussein Nili, Jiawei Yang, Doo Seok Jeong, Paul Beckett, Sharath Sriram, Damith Chinthana Ranasinghe, Omid Kavehei
2016 — conf
A high throughput, low latency null convention logic 16×16-bit multiplier.
ICSPCS
Prashant Dabholkar, Paul Beckett
2016 C conf
A low latency asynchronous Jenkins hash engine for IP lookup.
ISCAS
Prashant Dabholkar, Renuka Sovani, Paul Beckett
2016 — conf
An asynchronous short word length Delta-Sigma FIR filter for low power DSP.
ICSPCS
Renuka Sovani, Prashant Dabholkar, Paul Beckett
2016 C conf
Asynchronous interleaved scan architecture for on-line built-in self-test of null convention logic.
ISCAS
Nastaran Nemati, Mark C. Reed, Karl M. Fant, Paul Beckett
2016 A conf
Redesigning the Trans-disciplinary: Working Across Design, Craft and Technological Boundaries to Deliver an Integrated Wearable for Cardiac Monitoring.
Conference on Designing Interactive Systems
Leah Heiss, Paul Beckett, Amy Carr-Bottomley
2016 — conf
The Bel array: An asynchronous fine-grained co-processor for DSP.
ICSPCS
Andrew Przybylski, Kashfia Haque, Paul Beckett
2015 C conf
Design of asynchronous RISC CPU register-file Write-Back queue.
VLSI-SoC
Matthew M. Kim, Karl M. Fant, Paul Beckett
2015 — conf
Low Power Spatial Computing Using Null Convention Logic.
DSDIS
Kashfia Haque, Conrad Jakob, Paul Beckett
2014 — conf
A dual-rail LUT for reconfigurable logic using null convention logic.
ACM Great Lakes Symposium on VLSI
Jing Yu, Paul Beckett
2014 C conf
Design Techniques for NCL-Based Asynchronous Circuits on Commercial FPGA.
DSD
Matthew M. Kim, Paul Beckett
2014 J jnl
Radiation-Hard Field-Programmable Gate Arrays Configuration Technique Using Silicon on Sapphire.
IEEE Trans. Very Large Scale Integr. Syst.
Kashfia Haque, Paul Beckett
2013 J jnl
POWER-Area-Performance Characteristics of FPGA-based Sigma-Delta FIR Filters.
J. Signal Process. Syst.
Tayab Din Memon, Paul Beckett, Amin Z. Sadik
2012 J jnl
Reconfigurable Blocks Based on Balanced Ternary.
J. Signal Process. Syst.
Paul Beckett, Tayab Din Memon
2011 B conf
A Radiation Hard Lut Block with Auto-Scrubbing.
FPL
Kashfia Haque, Paul Beckett
2011 Misc conf
A SOI EEPROM Based Configuration Cell with Simple Scrubbing Detection.
VLSI Design
Kashfia Haque, Paul Beckett
2010 — conf
Run.
DELTA
Paul Beckett, Heiko Rudolph
2009 J jnl
Power scalability in a mesh-connected reconfigurable architecture.
ACM Trans. Embed. Comput. Syst.
Paul Beckett
2009 — conf
Towards a balanced ternary FPGA.
FPT
Paul Beckett
2008 J jnl
A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors.
IEEE Trans. Very Large Scale Integr. Syst.
Paul Beckett
2007 C conf
Soft Error Rate Estimation in Deep Sub-micron CMOS.
PRDC
Lianlian Zeng, Paul Beckett
2005 — conf
Low-power circuits using dynamic threshold devices.
ACM Great Lakes Symposium on VLSI
Paul Beckett
2005 — conf
Low-power spatial computing using dynamic threshold devices.
ISCAS (3)
Paul Beckett
2005 — conf
Why area might reduce power in nanoscale CMOS.
ISCAS (3)
Paul Beckett, Seth Copen Goldstein
2003 A conf
A Polymorphic Hardware Platform.
IPDPS
Paul Beckett
2003 — conf
Exploiting multiple functionality for nano-scale reconfigurable systems.
ACM Great Lakes Symposium on VLSI
Paul Beckett
2002 — conf
A fine-grained reconfigurable logic array based on double gate transistors.
FPT
Paul Beckett