Patrick Vuillod

18 papers A* 3A 8Journal 3Unranked 4

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	ML-Inspired Logic Synthesis: Improving Multiplier Circuits. MLCAD Yukio Miyasaka, Walter Lau Neto, Eleonora Testa, Anika Prasad, Michael Shuster, Reto Zimmermann, Patrick Vuillod, Alan Mishchenko, John Wawrzynek, Luca G. Amarù
2022	A*	`conf`	Improving LUT-based optimization for ASICs. DAC Walter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon
2022	A	`conf`	Majority-based Design Flow for AQFP Superconducting Family. DATE Giulia Meuli, Vinicius N. Possani, Rajinder Singh, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Patrick Vuillod, Luca G. Amarù, Scott Chase, Jamil Kawa, Giovanni De Micheli
2021	A*	`conf`	LUT-Based Optimization For ASIC Design Flow. DAC Luca Gaetano Amarù, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli
2020	J	`jnl`	Extending Boolean Methods for Scalable Logic Synthesis. IEEE Access Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2020	A*	`conf`	SAT-Sweeping Enhanced for Logic Synthesis. DAC Luca G. Amarù, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli
2019	A	`conf`	Scalable Boolean Methods in a Modern Synthesis Flow. DATE Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2018	A	`conf`	Improvements to boolean resynthesis. DATE Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli
2018	—	`conf`	Integrated ESOP Refactoring for Industrial Designs. ICECS Winston Haaswijk, Luca Gaetano Amarù, Patrick Vuillod, Jiong Luo, Mathias Soeken, Giovanni De Micheli
2017	A	`conf`	Enabling exact delay synthesis. ICCAD Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli
2017	A	`conf`	Logic optimization and synthesis: Trends and directions in industry. DATE Luca Gaetano Amarù, Patrick Vuillod, Jiong Luo, Janet Olson
2017	—	`conf`	Multi-level logic benchmarks: An exactness study. ASP-DAC Luca Gaetano Amarù, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
1998	J	`jnl`	Iterative remapping for logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Luca Benini, Patrick Vuillod, Giovanni De Micheli
1997	J	`jnl`	Clock Skew Optimization for Peak Current Reduction. J. VLSI Signal Process. Luca Benini, Patrick Vuillod, Alessandro Bogliolo, Giovanni De Micheli
1997	A	`conf`	Generalized matching from theory to application. ICCAD Patrick Vuillod, Luca Benini, Giovanni De Micheli
1997	A	`conf`	Re-mapping for low power under tight timing constraints. ISLPED Patrick Vuillod, Luca Benini, Giovanni De Micheli
1996	A	`conf`	Clock skew optimization for peak current reduction. ISLPED Patrick Vuillod, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli
1996	—	`conf`	Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification. ISSS Luca Benini, Patrick Vuillod, Claudionor José Nunes Coelho Jr., Giovanni De Micheli