Patrick Sittel

12 papers B 3Misc 1Journal 1Unranked 7
YearRankTypeTitle / Venue / Authors
2022 Misc conf
Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling.
FCCM
Nicolai Fiege, Patrick Sittel, Peter Zipf
2022 B conf
Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis.
FPL
Nicolai Fiege, Patrick Sittel, Peter Zipf
2022 J jnl
Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Patrick Sittel, Nicolai Fiege, John Wickerson, Peter Zipf
2022 B conf
Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals.
FPL
Nicolai Fiege, Patrick Sittel, Peter Zipf
2020 — conf
Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design.
ASP-DAC
Patrick Sittel, John Wickerson, Martin Kumm, Peter Zipf
2019 — conf
Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling.
Euro-Par
Julian Oppermann, Patrick Sittel, Martin Kumm, Melanie Reuter-Oppermann, Andreas Koch, Oliver Sinnen
2019 — conf
Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling.
ReConFig
Patrick Sittel, Nicolai Fiege, Martin Kumm, Peter Zipf
2018 — conf
Constant Matrix Multiplication with Ternary Adders.
ICECS
Martin Hardieck, Martin Kumm, Patrick Sittel, Peter Zipf
2018 B conf
ILP-Based Modulo Scheduling and Binding for Register Minimization.
FPL
Patrick Sittel, Martin Kumm, Julian Oppermann, Konrad Möller, Peter Zipf, Andreas Koch
2018 — conf
ScaLP: A Light-Weighted (MI)LP-Library.
MBMV
Patrick Sittel, Thomas Schönwälder, Martin Kumm, Peter Zipf
2017 — conf
High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits.
MBMV
Patrick Sittel, Martin Kumm, Konrad Möller, Martin Hardieck, Peter Zipf
2017 — conf
Model-based hardware design based on compatible sets of isomorphic subgraphs.
FPT
Patrick Sittel, Konrad Möller, Martin Kumm, Peter Zipf, Bogdan Pasca, Mark Jervis